MAX13202E Datasheet, PDF (5/9 Pages) Maxim Integrated Products – 2-/4-/6-/8-Channel, ±30kV ESD Protectors in μDFN

2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
During an ESD event, the current pulse rises from zero
to peak value in nanoseconds (Figure 3). For example,
in a ±15kV IEC-61000-4-2 Air-Gap Discharge ESD
event, the pulse current rises to approximately 45A in
1ns (di/dt = 45 x 10⁹). An inductance of only 10nH adds
an additional 450V to the clamp voltage. An inductance
of 10nH represents approximately 0.5in of board trace.
Regardless of the device’s specified diode clamp volt-
age, a poor layout with parasitic inductance significantly
increases the effective clamp voltage at the protected
signal line.
A low-ESR 0.1µF capacitor must be used between V_CC
and GND. This bypass capacitor absorbs the charge
transferred by a +14kV (MAX13204E/MAX13206E/
MAX13208E) and ±12kV (MAX13202E) IEC61000-4-2
Contact Discharge ESD event.
Ideally, the supply rail (V_CC) would absorb the charge
caused by a positive ESD strike without changing its
regulated value. In reality, all power supplies have an
effective output impedance on their positive rails. If a
power supply’s effective output impedance is 1Ω, then
by using V = I × R, the clamping voltage of V_C increas-
es by the equation V_C = I_ESD x R_OUT. An ±8kV
IEC 61000-4-2 ESD event generates a current spike of
24A, so the clamping voltage increases by V_C = 24A ×
1Ω, or V_C = 24V. Again, a poor layout without proper
bypassing increases the clamping voltage. A ceramic
chip capacitor mounted as close to the MAX13202E/
MAX13204E/MAX13206E/MAX13208E V_CC pin is the
best choice for this application. A bypass capacitor
should also be placed as close to the protected device
as possible.
±30kV ESD Protection
ESD protection can be tested in various ways. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E are
characterized for protection to the following limits:
• ±15kV using the Human Body Model
• ±14kV (MAX13204E/MAX13206E/MAX13208E) and
±12kV (MAX13202E) using the Contact Discharge
method specified in IEC 61000-4-2
• ±30kV using the IEC 61000-4-2 Air-Gap Discharge
method
ESD Test Conditions
ESD performance depends on a number of conditions.
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
R_C
1MΩ
R_D
1.5kΩ
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
100pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 4. Human Body ESD Test Model
I
100%
90%
10%
tR = 0.7ns to 1ns
30ns
60ns
I_P 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
t
0 _tRL
TIME
t_DL
CURRENT WAVEFORM
Figure 3. IEC 61000-4-2 ESD Generator Current Waveform
Figure 5. Human Body Model Current Waveform
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