MAX1304_11 Datasheet, PDF (6/37 Pages) Maxim Integrated Products – 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +5V, V_DVDD = +3V, V_AGND = V_DGND = 0V, V_REF = V_REFMS = +2.5V (external reference), C_REF = C_REFMS = 0.1µF, C_REF+ =
C_REF- = 0.1µF, C_REF+-to-REF- = 2.2µF || 0.1µF, C_COM = 2.2µF || 0.1µF, C_MSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
lar devices), f_CLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T_A = T_MIN to T_MAX,
unless otherwise noted. Typical values are at T_A = +25°C. See Figures 3 and 4.)
PARAMETER
Input-Data Setup Time
Input-Data Hold Time
External CLK Period
External CLK High Period
SYMBOL
CONDITIONS
t_DTW
t_WTD
Figure 6
Figure 6
t_CLK Figures 8, 9
t_CLKH
Logic sensitive to rising edges,
Figures 8, 9
MIN TYP MAX UNITS
10
ns
10
ns
0.05
10.00 µs
20
ns
External CLK Low Period
External Clock Frequency
Internal Clock Frequency
CONVST High to CLK Edge
t_CLKL
f_CLK
f_INT
t_CNTC
Logic sensitive to rising edges,
Figures 8, 9
(Note 11)
Figures 8, 9
20
ns
0.1
20
MHz
15
MHz
20
ns
Note 1: For the MAX1304/MAX1305/MAX1306, V_IN = 0 to +5V. For the MAX1308/MAX1309/MAX1310, V_IN = -5V to +5V. For the
MAX1312/MAX1313/MAX1314, V_IN = -10V to +10V.
Note 2: All channel performance is guaranteed by correlation to a single channel test.
Note 3: The analog input resistance is terminated to an internal bias point (Figure 5). Calculate the analog input current using:
I_{CH _}
=
V_{CH_} − V_BIAS
R _{CH _}
for V_{CH_} within the input voltage range.
Note 4: Throughput rate is given per channel. Throughput rate is a function of clock frequency (f_CLK). The external clock through-
put rate is specified with f_CLK = 16.67MHz and the internal clock throughput rate is specified with f_CLK = 15MHz. See the
Data Throughput section for more information.
Note 5: The REF input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF input current using:
I_REF
=
V_REF − 2.5V
R_REF
for V_REF within the input voltage range.
Note 6: The REF_MS input resistance is terminated to an internal +2.5V bias point (Figure 2). Calculate the REF_MS input current using:
I_REFMS
=
V_REFMS − 2.5V
R_REFMS
for V_REFMS within the input voltage range.
Note 7: All analog inputs are driven with a -0.4dBFS 500kHz sine wave.
Note 8: Shutdown current is measured with the analog input unconnected. The large amplitude of the maximum shutdown current
specification is due to automated test equipment limitations.
Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor droop.
Note 10: CS to WR and CS to RD are internally AND together. Setup and hold times do not apply.
Note 11: Minimum CLK frequency is limited only by the internal T/H droop rate. Limit the time between the rising edge of CONVST
and the falling edge of EOLC to a maximum of 1ms.
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