MAX1304_11 Datasheet, PDF (5/37 Pages) Maxim Integrated Products – 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +5V, V_DVDD = +3V, V_AGND = V_DGND = 0V, V_REF = V_REFMS = +2.5V (external reference), C_REF = C_REFMS = 0.1µF, C_REF+ =
C_REF- = 0.1µF, C_REF+-to-REF- = 2.2µF || 0.1µF, C_COM = 2.2µF || 0.1µF, C_MSV = 2.2µF || 0.1µF (unipolar devices), MSV = AGND (bipo-
lar devices), f_CLK = 16.67MHz 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T_A = T_MIN to T_MAX,
unless otherwise noted. Typical values are at T_A = +25°C. See Figures 3 and 4.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
MAX1304/MAX1305/MAX1306,
all channels selected
1.3
2.6
Digital Supply Current
(C_LOAD = 100pF) (Note 7)
I_DVDD
Shutdown Current
(Note 8)
I_AVDD
I_DVDD
Power-Supply Rejection Ratio
PSRR
TIMING CHARACTERISTICS (Figure 1)
Time to First Conversion Result
t_CONV
MAX1308/MAX1309/MAX1310,
all channels selected
MAX1312/MAX1313/MAX1314,
all channels selected
SHDN = DVDD, V_CH = open
SHDN = DVDD, RD = WR = high
V_AVDD = +4.75V to +5.25V
Internal clock, Figure 7
External clock, Figure 8
Time to Subsequent Conversions
t_NEXT
Internal clock, Figure 7
External clock, Figure 8
1.3
2.6
mA
1.3
2.6
0.6
10
µA
0.02
1
50
dB
800
900
ns
12
CLK
Cycles
200
225
ns
3
CLK
Cycles
CONVST Pulse-Width Low
(Acquisition Time)
CS Pulse Width
RD Pulse-Width Low
RD Pulse-Width High
WR Pulse-Width Low
CS to WR
WR to CS
CS to RD
RD to CS
Data Access Time
(RD Low to Valid Data)
Bus Relinquish Time (RD High)
CLK Rise to EOC Delay
CLK Rise to EOLC Fall Delay
CONVST Fall to EOLC Rise Delay
EOC Pulse Width
t_ACQ (Note 9) Figures 6–10
t_CS
t_RDL
t_RDH
t_WRL
t_CTW
t_WTC
t_CTR
t_RTC
Figure 6
Figures 7, 8, 9
Figures 7, 8, 9
Figure 6
Figure 6
Figure 6
Figures 7, 8, 9
Figures 7, 8, 9
t_ACC Figures 7, 8, 9
t_REQ Figures 7, 8, 9
t_EOCD Figure 8
t_EOLCD Figure 8
t_CVEOLCD Figures 7, 8, 9
Internal clock, Figure 7
t_{EOC External clock, Figure 8}
0.1
1000.0 µs
30
ns
30
ns
30
ns
30
ns
(Note 10)
ns
(Note 10)
ns
(Note 10)
ns
(Note 10)
ns
30
ns
5
30
ns
20
ns
20
ns
20
ns
50
ns
1
CLK
Cycle
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