MAX1304_11 Datasheet, PDF (14/37 Pages) Maxim Integrated Products – 8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs with ±10V, ±5V

8-/4-/2-Channel, 12-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
Pin Description (continued)
MAX1304
MAX1308
MAX1312
20
21
22
24, 39
25, 38
26
27
28
29
30
31
32
33
34
35
36
37
40
41
42
43
PIN
MAX1305
MAX1309
MAX1313
20
21
22
24, 39
25, 38
26
27
28
29
30
31
32
33
34
35
36
37
40
41
42
43
MAX1306
MAX1310
MAX1314
20
21
22
24, 39
25, 38
26
27
28
29
30
31
32
33
34
35
36
37
40
41
42
43
NAME
FUNCTION
REF+
Positive Reference Bypass. Bypass REF+ with a 0.1µF capacitor to AGND. Also
bypass REF+ to REF- with a 2.2µF and a 0.1µF capacitor.
V_REF+ = V_COM + V_REF/2.
COM
Reference Common Bypass. Bypass COM to AGND with a 2.2µF and a 0.1µF
capacitor. V_COM = 13/25 x AVDD.
REF-
Negative Reference Bypass. Bypass REF- with a 0.1µF capacitor to AGND.
Also bypass REF- to REF+ with a 2.2µF and a 0.1µF capacitor.
V_REF- = V_COM - V_REF/2.
DGND ^{Digital Ground. DGND is the power return for DVDD. Connect all DGND}
pins together.
DVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
EOC
EOLC
RD
WR
Digital Power Input. DVDD powers the digital section of the converter, including
the parallel interface. Apply +2.7V to +5.25V to DVDD. Bypass DVDD to DGND
with a 0.1µF capacitor. Connect all DVDD pins together.
Digital I/O 0 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 1 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 2 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 3 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 4 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 5 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 6 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital I/O 7 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or CS = 1.
Digital Output 8 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
Digital Output 9 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
Digital Output 10 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
Digital Output 11 of 12-Bit Parallel Data Bus. High impedance when RD = 1 or
CS = 1.
End-of-Conversion Output. EOC goes low to indicate the end of a conversion. It
returns high on the next rising CLK edge or the falling CONVST edge.
End-of-Last-Conversion Output. EOLC goes low to indicate the end of the
last conversion. It returns high when CONVST goes low for the next
conversion sequence.
Read Input. Pulling RD low initiates a read command of the parallel data bus.
Write Input. Pulling WR low initiates a write command for configuring the device
with D0–D7.
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