MAX1169N Datasheet, PDF (6/20 Pages) Maxim Integrated Products – 58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP

58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(AV_DD = +4.75V to +5.25V, DV_DD = +2.7V to +5.5V, f_SCL = 1.7MHz (33% duty cycle), f_SAMPLE = 58.6ksps, V_REF = +4.096V, external ref-
erence applied to REF, REFADJ = AV_DD, C_REF = 10µF, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
Note 9: A master device must provide a data hold time for SDA (referred to V_IL of SCL) in order to bridge the undefined region of
SCL’s falling edge (see Figure 1).
Note 10: C_B = total capacitance of one bus line in pF. t_R and t_F measured between 0.3 ✕ DV_DD and 0.7 ✕ DV_DD.
Note 11: f_SCL must meet the minimum clock low time plus the rise/fall times.
A. F/S-MODE I²C SERIAL INTERFACE TIMING
SDA
t_SU,DAT
t_LOW
t_HD,DAT
t_SU,STA
SCL
S
t_HD,STA
t_HIGH
t_R
t_F
B. HS-MODE I²C SERIAL INTERFACE TIMING
SDA
t_SU,DAT
t_LOW
SCL
S
t_HD,STA
t_RCL
t_HIGH
t_HD,DAT
t_FCL
PARAMETERS ARE MEASURED FROM 30% TO 70%.
Figure 1. I²C Serial Interface Timing
t_SU,STA
HS-MODE
t_HD,STA
Sr
A
t_HD,STA
Sr
A
t_R
t_F
t_BUF
t_SU,STO
P
t_RDA
S
t_FDA
t_BUF
t_SU,STO
t_RCL1
P
S
F/S-MODE
DIGITAL
I/O
V_DD
I_OL = 3mA
V_OUT
400pF
I_OH = 0mA
Figure 2. Load Circuit
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