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MAX1169N Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP
58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.5V, fSCL = 1.7MHz (33% duty cycle), fSAMPLE = 58.6ksps, VREF = +4.096V, external ref-
erence applied to REF, REFADJ = AVDD, CREF = 10µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Current
±10
µA
Input Capacitance
15
pf
POWER REQUIREMENTS (AVDD, AGND, DVDD, DGND)
Analog Supply Voltage
AVDD
4.75
5.25
V
Digital Supply Voltage
DVDD
2.7
5.5
V
Internal reference
(powered down
between conversions,
R/W = 0)
fSAMPLE = 58.6ksps
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
1.8
2.5
mA
0.7
40
µA
0.4
5
Analog Supply Current
IAVDD
Internal reference
(always on, R/W = 1)
fSAMPLE = 58.6ksps
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
1.8
2.5
mA
1.4
1.1
µA
0.4
5
External reference
(REFADJ = AVDD)
fSAMPLE = 58.6ksps
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
0.90
1.8
mA
0.36
40
µA
0.4
5
fSAMPLE = 58.6ksps
Digital Supply Current
IDVDD
fSAMPLE = 10ksps
fSAMPLE = 1ksps
Shutdown
Power-Supply Rejection Ratio
PSRR AVDD = 5V ±5%, full-scale input (Note 8)
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figure 1a and Figure 2)
260 400
65
µA
6
0.2
5
5
16 LSB/V
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time for Start Condition
Low Period of the SCL Clock
High Period of the SCL Clock
tHD, STA
tLOW
tHIGH
0.6
µs
1.3
µs
0.6
µs
Setup Time for a Repeated
START Condition (Sr)
tSU, STA
0.6
µs
Data Hold Time
Data Setup Time
tHD, DAT (Note 9)
tSU, DAT
0
900
ns
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Note 10)
20 + 0.1CB
300
ns
Fall Time of SDA Transmitting
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
tF
tSU, STO
CB
tSP
(Note 10)
20 + 0.1CB
0.6
300
ns
µs
400
pF
50
ns
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