MAX1169N Datasheet, PDF (13/20 Pages) Maxim Integrated Products – 58.6ksps, 16-Bit, 2-Wire Serial ADC in a 14-Pin TSSOP

58.6ksps, 16-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
where R_SOURCE is the analog input source impedance,
f_SCL is the maximum system SCL frequency, N is 16
(the number of bits of resolution), C_IN is 35pF (the sum
of C_T/H and input stray capacitance), and R_IN is 800Ω
(the T/H switch resistances).
To improve the input-signal bandwidth under AC
conditions, drive AIN with a wideband buffer
(>4MHz) that can drive the ADC’s input capacitance
and settle quickly (see the Input Buffer section).
An RC filter at AIN reduces the input track-and-hold
switching transient by providing charge for C_T/H.
Analog Input Bandwidth
The MAX1169 features input-tracking circuitry with a
4MHz small-signal bandwidth. The 4MHz input band-
width makes it possible to digitize high-speed transient
events and measure periodic signals with bandwidths
exceeding the ADC’s sampling rate by using under-
sampling techniques. Use anti-alias filtering to avoid
high-frequency signals being aliased into the frequency
band of interest.
Analog Input Range and Protection
Internal electrostatic discharge (ESD) protection diodes
clamp AIN, REF, and REFADJ to AV_DD and AGNDS/
AGND (Figure 6). These diodes allow the analog inputs
to swing from (AGND - 0.3V) to (AV_DD + 0.3V) without
causing damage to the device. For accurate conver-
sions, the inputs must not go more than 50mV beyond
their rails.
If the analog inputs exceed 300mV beyond their
rails, limit the current to 2mA.
Internal Clock
The MAX1169 contains an internal 4MHz oscillator that
drives the SAR conversion clock. During conversion, SCL
is held low (clock stretching). An internal register stores
data when the conversion is in progress. When the
MAX1169 releases SCL, the master reads the conversion
results at any clock rate up to 1.7MHz (Figure 11).
Digital Interface
The MAX1169 features an I²C-compatible, 2-wire serial
interface consisting of a bidirectional serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate bidirectional communication between the
MAX1169 and the master at rates up to 1.7MHz. The
master (typically a microcontroller) initiates data trans-
fer on the bus and generates SCL.
SDA and SCL require pullup resistors (500Ω or greater,
Figure 4). Optional resistors (24Ω) in series with SDA
and SCL protect the device inputs from high-voltage
spikes on the bus lines. Series resistors also minimize
crosstalk and undershoot of the bus signals.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. Nine clock cycles are required to transfer the
data into or out of the MAX1169. The data on SDA must
remain stable during the high period of the SCL clock
pulse as changes in SDA while SCL is high are control
signals (see the START and STOP Conditions section).
Both SDA and SCL idle high.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), a high-to-low transition on SDA with SCL high.
The master terminates a transmission with a STOP con-
dition (P), a low-to-high transition on SDA while SCL is
high (Figure 7). The STOP condition frees the bus and
places all devices in F/S mode (see the Bus Timing
section). Use a repeated START condition (Sr) in place
of a STOP condition to leave the bus active and in its
current timing mode (see the HS Mode section).
*R_SOURCE
AIN
HOLD
C_T/H
ANALOG
SIGNAL
SOURCE
TRACK
AGNDS
REF
MAX1169
CAPACITIVE
DAC
AV_DD
AIN
REF
REFADJ
AGNDS
MAX1169
*MINIMIZE R_SOURCE TO ALLOW THE TRACK-AND-HOLD CAPACITANCE (C_T/H) TO
CHARGE TO THE ANALOG SIGNAL SOURCE VOLTAGE WITHIN THE ALLOTTED TIME (t_ACQ).
AGND
Figure 5. Equivalent Input Circuit
Figure 6. Internal Protection Diodes
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