English
Language : 

MAX1167BE Datasheet, PDF (6/30 Pages) Maxim Integrated Products – Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters
◁
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
TIMING CHARACTERISTICS (Figures 1, 2, 8, and 16)
(AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, fSCLK = 4.8MHz external clock (50% duty cycle), 24 clocks/conversion
(200ksps), external VREF = +4.096V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Acquisition Time
tACQ External clock (Note 6)
729
ns
SCLK to DOUT Valid
tDO
CDOUT = 30pF
100
ns
CS Fall to DOUT Enable
tDV
CDOUT = 30pF
100
ns
CS Rise to DOUT Disable
CS Pulse Width
tTR
tCSW
CDOUT = 30pF
80
ns
100
ns
CS to SCLK Setup
SCLK rise
tCSS
SCLK fall (DSP)
100
ns
CS to SCLK Hold
tCSH
SCLK rise
SCLK fall (DSP)
0
ns
Conversion
93
SCLK High Pulse Width
tCH
Duty cycle 45% to 55%
Data transfer
93
ns
Conversion
93
SCLK Low Pulse Width
tCL
Duty cycle 45% to 55%
ns
Data transfer
93
SCLK Period
tCP
209
ns
DIN to SCLK Setup
SCLK rise
tDS
SCLK fall (DSP)
100
ns
DIN to SCLK Hold
SCLK rise
tDH
SCLK fall (DSP)
0
ns
CS Falling to DSPR Rising
tDF
100
ns
DSPR to SCLK Falling Setup
tFSS
100
ns
DSPR to SCLK Falling Hold
tFSH
0
ns
Note 1: AVDD = DVDD = +5.0V.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been
calibrated.
Note 3: Offset and reference errors nulled.
Note 4: DC voltage applied to on channel, and a full-scale 1kHz sine wave applied to off channels.
Note 5: Conversion time is measured from the rising edge of the 8th external SCLK pulse to EOC transition minus tACQ in 8-bit
data-transfer mode.
Note 6: See Figures 10 and 17.
Note 7: fSCLK = 4.8MHz, fINTCLK = 4.0MHz. Sample rate is calculated with the formula fs = n1 (n2 / fSCLK + n3 / fINTCLK)-1 where:
n1 = number of scans, n2 = number of SCLK cycles, and n3 = number of internal clock cycles (see Figures 11–14).
Note 8: Guaranteed by design; not production tested.
Note 9: Internal reference and buffer are left on between conversions.
Note 10: Defined as the change in the positive full scale caused by a ±5% variation in the nominal supply voltage.
6 _______________________________________________________________________________________
 ▷