MAX1167BE Datasheet, PDF (20/30 Pages) Maxim Integrated Products – Multichannel, 16-Bit, 200ksps Analog-to-Digital Converters

Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
CS
1
SCLK
INTERNAL
CLK
89
16
2
DIN
DATA
XXXXXXXX
DOUT
13
32
34
17
45
64
MSB
48
LSB
X
EOC
ADC
STATE
,
X = DON T CARE
t_ACQ
t_CONV
t_ACQ
t_CONV
POWER-DOWN
Figure 15. SPI Internal Clock Mode, 16-Bit Data-Transfer Mode, Scan Mode for Two Conversions, Conversion Timing (MAX1168 Only)
tCSW
CS
...
DSPR
tDF
tFSS
...
tFSH
tCSS
tCL
tCH
tCSH
SCLK
...
tCP
tDS
tDH
DIN
...
tDV
tDO
tTR
DOUT
...
Figure 16. Detailed DSP-Interface Timing (MAX1168 Only)
Internal Clock 16-Bit-Wide Data-Transfer and Scan
Mode (MAX1168 Only)
Force DSPR high and DSEL low for the SPI/QSPI/
MICROWIRE interface mode. The falling edge of CS
wakes the analog circuitry and allows SCLK to clock in
data (Figure 13). DOUT changes from high-Z to logic
low after CS is brought low. Input data latches on the
rising edge of SCLK. The command/configuration/con-
trol register begins reading DIN on the first SCLK rising
edge and ends on the rising edge of the 8th SCLK
cycle. The MAX1168 selects the proper channel for
conversion on the rising edge of the 3rd SCLK cycle.
The internal oscillator activates 125ns after the rising
edge of the 16th SCLK cycle. Turn off the external clock
while the internal clock is on. Turning off SCLK ensures
lowest noise performance during acquisition.
Acquisition begins on the 2nd rising edge of the inter-
nal clock and ends on the falling edge of the 18th inter-
nal clock cycle. Each bit of the conversion result shifts
into memory as it becomes available. The conversion
result is available (MSB first) at DOUT on the falling
edge of EOC. The internal oscillator and analog circuitry
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