DS1124_09 Datasheet, PDF (6/10 Pages) Maxim Integrated Products – 5.0V 8-Bit Programmable Timing Element

5.0V 8-Bit Programmable
Timing Element
Block Diagram
IN
PROGRAMMABLE
OUT
DELAY
8
8-BIT LATCH
E
8
8-BIT SHIFT
REGISTER
Q
CLK
DS1124
D
Detailed Description
The DS1124 is an 8-bit programmable delay line that
can be adjusted between 256 different delay intervals.
The DS1124 architecture (see Figure 2) allows some
signals to be delayed by more than one period, which
lets the phase of the signal to be adjusted up to a full
360°. Programming is performed by a 3-wire serial
interface. Using the 3-wire interface, it is possible to
cascade multiple devices together for systems requir-
ing multiple programmable delays without using addi-
tional I/O resources.
Using the Serial Programming Interface
Serial mode operates similar to a shift register. When the
E pin is set at a high logic level, it enables the shift regis-
ter and CLK clocks the data, D, into the register one bit at
a time starting with the most significant bit. After all 8 bits
are shifted into the DS1124, E must be pulled low to end
the data transfer and activate the new value. A settling
time (t_EDV) is required after E is pulled low before the
signal delay will meet its specified accuracy. A timing
diagram for the serial interface is shown in Figure 3.
The 3-wire interface also has an output (Q) that can be
used to cascade multiple 3-wire devices, and it can be
used to read the current value of the devices on the
bus. To read the current values stored by the 3-wire
device(s), the latch must be enabled and the value of Q
must be read and then written back to D before the reg-
ister is clocked. This causes the current value of the
register to be written back into the DS1124 as it is
being read. This can be accomplished in a couple of
different ways. If the microprocessor has an I/O pin that
is high impedance when set as an input, a feedback
resistor (R_FB, generally between 1kΩ and 10kΩ) can be
used to write the data on Q back to D as the value is
read, see Figure 4A. If the microprocessor has an inter-
nal pullup on its I/O pins, or only offers separate input
and output pins, the value in the register can still be
read. The circuit shown in Figure 4B allows the Q val-
ues to read by the microprocessor, which must write
the Q value to D before it can clock the bus to read the
next bit. If the Q values are read without writing them to
D (with the pullup or otherwise), the read will be
destructive. A destructive read cycle likely results in an
undesirable change in the delay setting.
IN
OUT
256 CONTROL LINES
t_STEP
t_STEP
t_STEP
t_STEP
256 LINE DECODER
8-BIT LATCH VALUE
255 UNIT DELAY CELLS
DS1124
Figure 2. Conceptual Design
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