DS1124_09 Datasheet, PDF (3/10 Pages) Maxim Integrated Products – 5.0V 8-Bit Programmable Timing Element

5.0V 8-Bit Programmable
Timing Element
AC ELECTRICAL CHARACTERISTICS (continued)
(V_CC = +4.75V to +5.25V, T_A = -40°C to +85°C, unless otherwise noted.)
PARAMETER
E to Delay Valid
E to Delay Invalid
Power-Up Time
Delay Step Size
Step 0 Delay
Step 0 Delay Initial Accuracy
Step 0 Voltage Variation
Step 0 Temperature Variation
Step 0 Temperature Variation
Step 255 Delay
Step 255 Delay Initial Accuracy
Step 255 Voltage Variation
Step 255 Temperature Variation
Step 255 Temperature Variation
SYMBOL
CONDITIONS
t_EDV
t_EDX
t_PU
t_STEP T_A = +25°C
t_D0 (Note 2)
V_CC = 5V, T_A = +25°C
t_D255
0°C to +70°C
-40°C to +85°C
(Note 2)
V_CC = 5V, T_A = +25°C
0°C to +70°C
-40°C to +85°C
MIN
0
-0.75
17
-0.6
-0.4
-1
-1
77
-0.6
-0.4
-3
-5
TYP
+0.25
20
83.75
MAX
50
100
+1
23
+0.6
+0.4
+1
+1
88
+0.6
+0.4
+3
+5
UNITS
μs
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Integral Nonlinearity
(Deviation from Straight Line)
t_ERR V_CC = 5V, T_A = +25°C (Note 3)
-2
0
+2
ns
Minimum Input Pulse Width
Minimum Input Period
Input Rise and Fall Times
t_WI
t_PER
t_R, t_F
(Note 4)
(Note 5)
(Note 6)
40
ns
80
ns
0
1
μs
Note 1: All voltages are referenced to ground.
Note 2: Measured from rising edge of the input to the rising edge of the output. The programmed delay, t_D, can be programmed
with values from 0 to 255. See Figure 1.
Note 3: See the Integral Nonlinearity section and Figure 5.
Note 4: This is the minimum allowable interval between transitions on the input to ensure accurate device operation. This parameter
can be violated but timing accuracy may be impaired and ultimately very narrow pulse widths will result in no output from
the device. See Figure 1.
Note 5: When a 50% duty cycle input clock is used, this defines the highest usable clock frequency. When asymmetrical clock
inputs are used, the maximum usable clock frequency must be reduced to conform to the minimum input pulse-width
requirement. See Figure 1.
Note 6: Faster rise and fall times give the greatest accuracy in measured delay. Slow edges (outside the specification maximum)
can result in erratic operations.
IN
IN
OUT
DS1124
OUT
TIMING REFERENCED TO 1.5V.
Figure 1. Delay Timing Diagram
tWI
tD0
tD0
tD
tWI
tD
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