MAX1190 Datasheet, PDF (5/21 Pages) Maxim Integrated Products – Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 3.3V; OV_DD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10kΩ resistor; V_REFIN = 2.048V; V_IN = 2V_P-P (differential with respect to COM); C_L = 10pF at digital outputs; f_CLK = 120MHz; T_A =
T_MIN to T_MAX, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization;
typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Analog Supply Current
I_VDD
Operating, f_{INA and B} = 20.01MHz at
-0.5dB FS
Sleep mode
149 185
mA
3
Output Supply Current
I_OVDD
Shutdown, clock idle, PD = OE = OV_DD
Operating, f_{INA and B} = 20.01MHz at -0.5dB
FS; see Typical Operating Characteristics
section, Digital Supply Current vs. Analog
Input Frequency
1
15
µA
16
mA
Analog Power Dissipation
Power-Supply Rejection Ratio
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Time
OE Fall to Output Enable Time
OE Rise to Output Disable Time
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
PDISS
PSRR
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Operating, f_{INA and B} = 20.01MHz at
-0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OV_DD
Offset, V_DD ±5%
Gain, V_DD ±5%
t_DO
t_ENABLE
t_DISABLE
t_CH
t_CL
t_WAKE
C_L = 20pF (Note 3)
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
Clock period: 8.34ns; see Typical Operating
Characteristics section, AC Performance vs.
Clock Duty Cycle
Wake up from sleep mode (Note 4)
Wake up from shutdown mode (Note 4)
100
2
10
492 611
10
3.3
50
±3.4
±0.81
µA
mW
mW
µW
mV/V
%/V
4.8
7.4
ns
4.7
ns
1.2
ns
4.17
ns
4.17
ns
0.65
µs
1.2
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
Gain Matching
Phase Matching
f_{INA or B} = 20.01MHz at -0.5dB FS
f_{INA or B} = 20.01MHz at -0.5dB FS (Note 5)
f_{INA or B} = 20.01MHz at -0.5dB FS (Note 6)
-71
dBc
0.08 ±0.2
dB
0.8
Degrees
Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power.
Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor.
Note 3: Digital outputs settle to V_IH, V_IL. Parameter guaranteed by design.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda-
mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of
the calculated FFT. The data from both ADC channels must be captured simultaneously during this test.
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