MAX1190 Datasheet, PDF (10/21 Pages) Maxim Integrated Products – Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
40
D5A Three-State Digital Output, Bit 5, Channel A
41
D6A Three-State Digital Output, Bit 6, Channel A
42
D7A Three-State Digital Output, Bit 7, Channel A
43
D8A Three-State Digital Output, Bit 8, Channel A
44
D9A Three-State Digital Output, Bit 9 (MSB), Channel A
45
REFOUT Internal Reference Voltage Output. Can be connected to REFIN through a resistor or a resistor-divider.
46
REFIN Reference Input. V_REFIN = 2 × (V_REFP - V_REFN). Bypass to GND with a >0.1µF capacitor.
47
REFP Positive Reference I/O. Conversion range is ±(V_REFP - V_REFN). Bypass to GND with a >0.1µF capacitor.
48
REFN Negative Reference I/O. Conversion range is ±(V_REFP - V_REFN). Bypass to GND with a >0.1µF capacitor.
Detailed Description
The MAX1190 uses a nine-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half-clock cycle.
Including the delay through the output latch, the total
clock-cycle latency is five clock cycles.
Flash ADCs convert the held input voltages into a digi-
tal code. Internal MDACs convert the digitized results
back into analog voltages, which are then subtracted
from the original held input signals. The resulting error
signals are then multiplied by 2, and the residues are
passed along to the next pipeline stages, where the
process is repeated until the signals have been
processed by all nine stages.
Input Track-and-Hold Circuits
Figure 2 displays a simplified functional diagram of the
input T/H circuits in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuits sample the input
signals onto the two capacitors (C2a and C2b) through
switches S4a and S4b. S2a and S2b set the common
mode for the amplifier input, and open simultaneously
with S1, sampling the input waveform. Switches S4a,
S4b, S5a, and S5b are then opened before switches
S3a and S3b connect capacitors C1a and C1b to the
output of the amplifier and switch S4c is closed. The
resulting differential voltages are held on capacitors
C2a and C2b. The amplifiers are used to charge capac-
itors C1a and C1b to the same values originally held on
C2a and C2b.
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
STAGE 1
STAGE 2
STAGE 8
2-BIT FLASH
ADC
STAGE 9
T/H
V_INA
DIGITAL ALIGNMENT LOGIC
10
DIGITAL ALIGNMENT LOGIC
T/H
10
D9A–D0A
V_INB
V_INA = INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED)
V_INB = INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED)
D9B–D0B
Figure 1. Pipelined Architecture—Stage Blocks
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