MAX1190 Datasheet, PDF (13/21 Pages) Maxim Integrated Products – Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1190
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 3 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data (D0A/B–D9A/B), Output
Data Format Selection (T/B), Output
Enable (OE)
All digital outputs, D0A–D9A (channel A) and D0B–D9B
(channel B), are TTL/CMOS-logic compatible. There is
a five-clock-cycle latency between any particular sam-
ple and its corresponding output data. The output cod-
ing can be chosen to be either straight offset binary or
two’s complement (Table 1) controlled by a single pin
(T/B). Pull T/B low to select offset binary and high to
activate two’s complement output coding. The capaci-
tive load on digital outputs D0A–D9A and D0B–D9B
should be kept as low as possible (<15pF) to avoid
large digital currents that could feed back into the ana-
log portion of the MAX1190, thereby degrading its
dynamic performance. Using buffers on the digital out-
puts of the ADCs can further isolate the digital outputs
from heavy capacitive loads. To further improve the
dynamic performance of the MAX1190, small series
resistors (e.g., 100Ω) can be added to the digital output
paths, close to the MAX1190.
Figure 4 displays the timing relationship between out-
put enable and data output valid, as well as power-
down/wakeup and data output valid.
Power-Down (PD) and Sleep
(SLEEP) Modes
The MAX1190 offers two power-save modes—sleep
mode and full power-down mode. In sleep mode
(SLEEP = 1), only the reference bias circuit is active
OE
OUTPUT
D9A–D0A
t_ENABLE
HIGH-Z
t_DISABLE
VALID DATA
HIGH-Z
OUTPUT
D9B–D0B
HIGH-Z
VALID DATA
HIGH-Z
Figure 4. Output Timing Diagram
(both ADCs are disabled), and current consumption is
reduced to 3mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Applications Information
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V_DD/2 output voltage for level-
shifting purposes. The input is buffered and then split
to a voltage follower and inverter. One lowpass filter per
amplifier suppresses some of the wideband noise
associated with high-speed operational amplifiers. The
user can select the R_ISO and C_IN values to optimize the
filter performance to suit a particular application. For
the application in Figure 5, a R_ISO of 50Ω is placed
before the capacitive load to prevent ringing and oscil-
lation. The 22pF C_IN capacitor acts as a small filter
capacitor.
Table 1. MAX1190 Output Codes For Differential Inputs
DIFFERENTIAL INPUT
VOLTAGE*
V_REF × 512/512
V_REF × 1/512
0
-V_REF × 1/512
-V_REF × 511/512
-V_REF × 512/512
*VREF = VREFP - VREFN
DIFFERENTIAL INPUT
+FULL SCALE - 1LSB
+1LSB
Bipolar Zero
-1LSB
-FULL SCALE + 1LSB
-FULL SCALE
STRAIGHT OFFSET BINARY
T/B = 0
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
TWO’S COMPLEMENT
T/B = 1
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
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