MAX1190 Datasheet, PDF (12/21 Pages) Maxim Integrated Products – Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC
with Internal Reference and Parallel Outputs
Analog Inputs and Reference
Configurations
The full-scale range of the MAX1190 is determined by the
internally generated voltage difference between REFP
(V_DD/2 + V_REFIN/4) and REFN (V_DD/2 - V_REFIN/4). The full-
scale range for both on-chip ADCs is adjustable through
the REFIN pin, which is provided for this purpose.
The MAX1190 provides three modes of reference oper-
ation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, connect the internal refer-
ence output REFOUT to REFIN through a resistor (e.g.,
10kΩ) or resistor-divider, if an application requires a
reduced full-scale range. For stability and noise filtering
purposes, bypass REFIN with a >10nF capacitor to
GND. In internal reference mode, REFOUT, COM,
REFP, and REFN become low-impedance outputs.
In buffered external reference mode, adjust the refer-
ence voltage levels externally by applying a stable and
accurate voltage at REFIN. In this mode, COM, REFP,
and REFN are outputs. REFOUT can be left open or
connected to REFIN through a >10kΩ resistor.
In unbuffered external reference mode, connect REFIN to
GND. This deactivates the on-chip reference buffers for
REFP, COM, and REFN. With their buffers shut down,
these nodes become high-impedance inputs and can be
driven through separate, external reference sources.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the Applications Information section.
Clock Input (CLK)
The MAX1190’s CLK input accepts a CMOS-compati-
ble clock signal. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). In particular,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant aperture jitter would limit the SNR per-
formance of the on-chip ADCs as follows:
SNR
=
20
×
log


2
×
π
×
1
f _IN×
t_AJ


where f_IN represents the analog input frequency and t_AJ
is the time of the aperture jitter. Clock jitter is especially
critical for undersampling applications. The clock input
should always be considered as an analog input and
routed away from any analog input or other digital signal
lines. The MAX1190 clock input operates with a voltage
threshold set to V_DD/2. Clock inputs with a duty cycle
other than 50%, must meet the specifications for high and
low periods as stated in the Electrical Characteristics.
ANALOG INPUT
5-CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
t_AD
CLOCK INPUT
DATA OUTPUT
D9A–D0A
t_DO
t_CH
t_CL
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
DATA OUTPUT
D9B–D0B
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
Figure 3. System Timing Diagram
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