MAX11606_11 Datasheet, PDF (5/22 Pages) Maxim Integrated Products – Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small Packages

Low-Power, 4-/8-/12-Channel, I²C,
10-Bit ADCs in Ultra-Small Packages
TIMING CHARACTERISTICS (Figure 1) (continued)
(V_DD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), V_DD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), V_REF = 2.048V
(MAX11607/MAX11609/MAX11611), V_REF = 4.096V (MAX11606/MAX11608/MAX11610), f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless other-
wise noted. Typical values are at T_A = +25°C. See Tables 1–5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Rise Time of SCL Signal
(Current Source Enabled)
t_RCL Measured from 0.3V_DD to 0.7V_DD
20
80
ns
Rise Time of SCL Signal after
Acknowledge Bit
t_RCL1 Measured from 0.3V_DD to 0.7V_DD
20
160
ns
Fall Time of SCL Signal
t_FCL Measured from 0.3V_DD to 0.7V_DD
20
Rise Time of SDA Signal
t_RDA Measured from 0.3V_DD to 0.7V_DD
20
Fall Time of SDA Signal
t_FDA Measured from 0.3V_DD to 0.7V_DD (Note 12)
20
Setup Time for STOP (P) Condition t_SU,_STO
160
Capacitive Load for Each Bus Line C_B
Pulse Width of Spike Suppressed
t_SP
(Notes 11 and 14)
0
80
ns
160
ns
160
ns
ns
400
pF
10
ns
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
All WLP devices are 100% production tested at T_A = +25°C. Specifications over temperature limits are guaranteed by
design and characterization.
For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at V_DD = 5V and the MAX11607/MAX11609/MAX11611
are tested at V_DD = 3V. All devices are configured for unipolar, single-ended inputs.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Offset nulled.
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion
time does not include acquisition time. SCL is the conversion clock in the external clock mode.
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to V_DD.
When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a
0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit).
ADC performance is limited by the converter’s noise floor, typically 300µV_P-P.
Note 10: Measured as follows for the MAX11607/MAX11609/MAX11611:
[ ] ^⎡
⎢
⎣
V_FS(3.6V) − V_FS(2.7V)
×
2^N −1^⎤
V_REF
⎥
⎦
(3.6V − 2.7V)
and for the MAX11606/MAX11608/MAX11610, where N is the number of bits:
[ ] ^⎡
⎢
⎣
V_FS(5.5V) − V_FS(4.5V)
×
2^N −1^⎤
V_REF
⎥
⎦
(5.5V − 4.5V)
Note 11: A master device must provide a data hold time for SDA (referred to V_IL of SCL) to bridge the undefined region of SCL’s
falling edge (see Figure 1).
Note 12: The minimum value is specified at T_A = +25°C.
Note 13: C_B = total capacitance of one bus line in pF.
Note 14: f_SCL must meet the minimum clock low time plus the rise/fall times.
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