MAX11606_11 Datasheet, PDF (15/22 Pages) Maxim Integrated Products – Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small Packages

Low-Power, 4-/8-/12-Channel, I²C,
10-Bit ADCs in Ultra-Small Packages
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
CS3¹ CS2¹ CS1 CS0 AIN0 AIN1 AIN2 AIN3² AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11²
0
0
0
0
+
-
0
0
0
1
-
+
0
0
1
0
+
-
0
0
1
1
-
+
0
1
0
0
+
-
0
1
0
1
-
+
0
1
1
0
+
-
0
1
1
1
-
+
1
0
0
0
+
-
1
0
0
1
-
+
1
0
1
0
+
-
1
0
1
1
-
+
1
1
0
0
RESERVED
1
1
0
1
RESERVED
1
1
1
0
RESERVED
1
1
1
1
RESERVED
1_{For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0.}
2_{When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX11606/MAX11607) or AIN10 and AIN11/REF}
(MAX11610/MAX11611) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011
returns the negative difference between AIN10 and GND. This does not apply to the MAX11608/MAX11609 as each provides separate
pins for AIN7 and REF. In differential scanning, the address increments by 2 until the limit set by CS3–CS1 has been reached.
Data Byte (Read Cycle)
A read cycle must be initiated to obtain conversion
results. Read cycles begin with the bus master issuing
a START condition followed by seven address bits and
a read bit (R/W = 1). If the address byte is successfully
received, the MAX11606–MAX11611 (slave) issues an
acknowledge. The master then reads from the slave.
The result is transmitted in two bytes; first six bits of the
first byte are high, then MSB through LSB are consecu-
tively clocked out. After the master has received the
byte(s), it can issue an acknowledge if it wants to con-
tinue reading or a not-acknowledge if it no longer wish-
es to read. If the MAX11606–MAX11611 receive a not-
acknowledge, they release SDA, allowing the master to
generate a STOP or a repeated START condition. See
the Clock Modes and Scan Mode sections for detailed
information on how data is obtained and converted.
Clock Modes
The clock mode determines the conversion clock and
the data acquisition and conversion time. The clock
mode also affects the scan mode. The state of the set-
up byte’s CLK bit determines the clock mode (Table 1).
At power-up, the MAX11606–MAX11611 are defaulted
to internal clock mode (CLK = 0).
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11606–MAX11611 use their internal oscillator as the
conversion clock. In internal clock mode, the MAX11606–
MAX11611 begin tracking the analog input after a valid
address on the eighth rising edge of the clock. On the
falling edge of the ninth clock, the analog signal is
acquired and the conversion begins. While converting the
analog input signal, the MAX11606–MAX11611 holds SCL
low (clock stretching). After the conversion completes, the
results are stored in internal memory. If the scan mode is
set for multiple conversions, they all happen in succession
with each additional result stored in memory. The
MAX11606/MAX11607 contain four 10-bit blocks of memo-
ry, the MAX11608/MAX11609 contain eight 10-bit blocks of
memory, and the MAX11610/MAX11611 contain twelve 10-
bit blocks of memory. Once all conversions are complete,
the MAX11606–MAX11611 release SCL, allowing it to be
pulled high. The master may now clock the results out
of the memory in the same order the scan conversion
has been done at a clock rate of up to 1.7MHz. SCL is
stretched for a maximum of 7.6µs per channel (see
Figure 10).
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