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| MAX11606_11 Datasheet, PDF (4/22 Pages) Maxim Integrated Products – Low-Power, 4-/8-/12-Channel, I2C, 10-Bit ADCs in Ultra-Small Packages | |||
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Low-Power, 4-/8-/12-Channel, I2C,
10-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V
(MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C. See Tables 1â5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio
PSRR Full-scale input (Note 10)
±0.01 ±0.5 LSB/V
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V
(MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless other-
wise noted. Typical values are at TA = +25°C. See Tables 1â5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
CONDITIONS
MIN TYP MAX UNITS
400 kHz
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF
1.3
µs
Hold Time for START (S) Condition
Low Period of the SCL Clock
High Period of the SCL Clock
tHD,STA
tLOW
tHIGH
Setup Time for a Repeated START
Condition (Sr)
tSU,STA
Data Hold Time
Data Setup Time
tHD,DAT (Note 11)
tSU,DAT
Rise Time of Both SDA and SCL
Signals, Receiving
tR
Measured from 0.3VDD to 0.7VDD
Fall Time of SDA Transmitting
tF
Measured from 0.3VDD to 0.7VDD (Note 12)
Setup Time for STOP (P) Condition tSU,STO
Capacitive Load for Each Bus Line CB
Pulse Width of Spike Suppressed
tSP
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 13)
Serial-Clock Frequency
fSCLH (Note 14)
Hold Time, Repeated START
Condition (Sr)
tHD,STA
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
20 + 0.1CB
0.6
160
µs
µs
µs
µs
900
ns
ns
300
ns
300
ns
µs
400
pF
50
ns
1.7 MHz
ns
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
tLOW
tHIGH
tSU,STA
320
ns
120
ns
160
ns
Data Hold Time
Data Setup Time
tHD,DAT (Note 11)
tSU,DAT
0
150
ns
10
ns
4 _______________________________________________________________________________________
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