MAX1111CE Datasheet, PDF (5/20 Pages) Maxim Integrated Products – 2.7V, Low-Power, Multichannel, Serial 8-Bit ADCs

+2.7V, Low-Power, Multichannel,
Serial 8-Bit ADCs
TIMING CHARACTERISTICS (Figures 8 and 9)
(V_DD = 2.7V to 5.5V, T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
Track/Hold Acquisition Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to SSTRB
CS Fall to SSTRB Output Enable
(Note 6)
CS Rise to SSTRB output
Disable (Note 6)
SSTRB Rise to SCLK Rise
(Note 6)
Wake-Up Time
SYMBOL
t_ACQ
t_DS
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSH
t_CH
t_CL
t _SSTRB
t_SDV
t_STR
CONDITIONS
Figure 1, C_LOAD = 100pF
Figure 1, C_LOAD = 100pF
Figure 2, C_LOAD = 100pF
C_LOAD = 100pF
Figure 1, external clock mode only,
C_LOAD = 100pF
Figure 2, external clock mode only,
C_LOAD = 100pF
t_SCK Figure 11, internal clock mode only
t_WAKE
External reference
Internal reference (Note 11)
MIN TYP MAX UNITS
1
µs
100
ns
0
ns
20
200
ns
240
ns
240
ns
100
ns
0
ns
200
ns
200
ns
240
ns
240
ns
240
ns
0
ns
20
µs
12
ms
Note 1: Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.
Note 2: See Typical Operating Characteristics.
Note 3: V_REFIN = 2.048V, offset nulled.
Note 4: On-channel grounded; sine wave applied to all off-channels.
Note 5: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: Guaranteed by design. Not subject to production testing.
Note 7: Common-mode range for the analog inputs is from AGND to V_DD.
Note 8: External load should not change during the conversion for specified accuracy.
Note 9: External reference at 2.048V, full-scale input, 500kHz external clock.
Note 10: Measured as | V_FS (2.7V) - V_FS (3.6V) |.
Note 11: 1µF at REFOUT; internal reference settling to 0.5 LSB.
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