MAX105 Datasheet, PDF (5/21 Pages) Maxim Integrated Products – Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(AV_CC = AV_CCI = AV_CCQ = AV_CCR = +5V, OV_CCI = OV_CCQ = +3.3V, AGND = AGNDI = AGNDQ = AGNDR = 0, OGNDI = OGNDQ
= 0, f_CLK = 802.816MHz, C_L= 1µF to AGND at REF, R_L = 100Ω ±1% applied to digital LVDS outputs, T_A = T_MIN to T_MAX, unless
otherwise noted. Typical values are at T_A = +25°C)
PARAMETER
DREADY Duty Cycle
LVDS Output Rise-Time
LVDS Output Fall-Time
LVDS Differential Skew
DREADY Rise-Time
DREADY Fall-Time
Primary Port Pipeline Delay
SYMBOL
t_RDATA
t_FDATA
t_SKEW1
t_RDREADY
t_FDREADY
t_PDP
CONDITIONS
(Notes 5, 13)
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
Any differential pair
Any two LVDS output signals except DREADY
20% to 80% (Notes 5, 13)
20% to 80% (Notes 5, 13)
MIN TYP MAX UNITS
47
53
%
200
500
ps
200
500
ps
<65
ps
<100
ps
200
500
ps
200
500
ps
5
Clock
Cycles
Auxiliary Port Pipeline Delay
t_PDA
6
Clock
Cycles
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
NL and DNL is measured using a sine-histogram method.
Input offset is the voltage required to cause a transition between codes 0 and -1.
Numbers provided are for DC-coupled case. The user has the choice of AC-coupling, in which case, the DC input
voltage level does not matter.
The peak-to-peak input voltage required, causing a full-scale digitized output when using a trigonometric curve-fitting
algorithm (e.g. FFT).
Guaranteed by design and characterization.
Common-mode rejection ratio is defined as the ratio of the change in the offset voltage to the change in the common-
mode voltage expressed in dB.
Measured with analog power supplies tied to the same potential.
Effective number of bits (ENOB) is computed from a curve-fit referenced to the theoretical full-scale range.
The clock and input frequencies are chosen so that there are 2041 cycles in an 8,192-long record.
Signal-to-noise-ratio (SNR) is measured both with the other channel idling and converting an out-of-phase signal.
The worst case number is presented. Harmonic distortion components two through five are excluded from the noise.
Harmonic distortion components two through five are included in the total harmonic distortion specification.
Both I and Q inputs are effectively tied together (e.g. driven by power splitter). Signal amplitude is -0.5dB FS at an input
frequency of f_IN = 200.0180 MHz.
Measured with a differential probe, 1pF capacitance.
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