MAX105 Datasheet, PDF (13/21 Pages) Maxim Integrated Products – Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
Table 1. Digital Output Codes Corresponding to a DC-Coupled Single-Ended Analog
Input
IN-PHASE INPUTS
(INI+, INQ+)
> +400mV + V_REF
+400mV - 0.5LSB + V_REF
0V + V_REF
-400mV + 0.5LSB + V_REF
< -400mV + V_REF
INVERTED INPUTS
(INI-, INQ-)
AC – Coupled to AGND_
AC – Coupled to AGND_
AC – Coupled to AGND_
AC – Coupled to AGND_
AC – Coupled to AGND_
OUT-OF-RANGE BIT
(DOR+, DOR-)
1
0
0
0
1
OUTPUT CODE
011111
011111
000000/111111
100000
100000
Table 2. Digital Output Codes Corresponding to a DC-Coupled Differential Analog Input
IN-PHASE INPUTS
(INI+, INQ+)
>+200mV + V_REF
+200mV - 0.25LSB + V_REF
0V + V_REF
-200mV + 0.25LSB + V_REF
<-200mV + V_REF
INVERTED INPUTS
(INI-, INQ-)
<-200mV + V_REF
-200mV + 0.25LSB + V_REF
0V + V_REF
+200mV - 0.25LSB + V_REF
>+200mV + V_REF
OUT-OF-RANGE BIT
(DOR+, DOR-)
1
0
0
0
1
OUTPUT CODE
011111
011111
000000/111111
100000
100000
MAX105 LVDS-outputs provide a typical ±270mV volt-
age swing around a common mode voltage of roughly
+1.2V, and must be differentially terminated at the far
end of each transmission line pair (true and comple-
mentary) with 100Ω.
Out-Of-Range Operation
A single output pair (DOR+, DOR-) is provided to flag
an out-of-range condition, if either the I or Q channel is
out-of-range, where out-of-range is above +FS or below
-FS. It features the same latency as the ADCs output
data and is demultiplexed in a similar fashion. With a
800MHz system clock, DOR+ and DOR- are clocked at
up to 400MHz.
Applications Information
Single-Ended Analog Inputs
The MAX105 is designed to work at full-speed for both
single-ended and differential analog inputs without sig-
nificant degradation in its dynamic performance. Both
input channels I (INI+, INI-) and Q (INQ+, INQ-) have
2kΩ impedance and allow for AC- and DC-coupled
input signals. In a typical DC-coupled single-ended
configuration (Table 1), the analog input signals enter
the analog input amplifier stages at the in-phase-input
pins INI+/INQ+, while the inverted phase input INI-
/INQ- pins are AC-coupled to AGNDI/AGNDQ. Single-
ended operation allows for an input amplitude of
800mV_p-p, centered around V_REF.
Differential Analog Inputs
To obtain +FS digital outputs with differential input drive
(Table 2), 400mV must be applied between INI+ (INQ+)
and INI- (INQ-). Midscale digital output codes occur
when there is no voltage difference between INI+
(INQ+) and INI- (INQ-). For a -FS digital output code
both in-phase (INI+, INQ+) and inverted input (INI-,
INQ-) must see -400mV.
Single-Ended to Differential
Conversion Using a Balun
An RF balun (Figure 3) provides an excellent solution to
convert a single-ended signal to a fully differential sig-
nal, required by the MAX105 for optimum performance.
At higher frequencies, the MAX105 provides better
SFDR and THD with fully differential input signals over
single-ended input signals. In differential input mode,
even-order harmonics are suppressed and each input
requires only half the signal-swing compared to single-
ended mode.
Clock Input
The MAX105 features clock inputs designed for either
single-ended or differential operation with very flexible
input drive requirements. The clock inputs (AC- or DC-
coupled) provide a 5kΩ input impedance to AV_CC/2
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