MAX105 Datasheet, PDF (14/21 Pages) Maxim Integrated Products – Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
50Ω
D
100pF
AGND
CLK+,
INI+,
INQ+
SIGNAL SOURCE ^A
50Ω
0°
0°
B
180°
C
0°
50Ω
50Ω*
AGND
100pF
CLK-,
INI-,
INQ-
AGND
*TERMINATION OF THE UNUSED INPUT/OUTPUT (WITH 50Ω TO AGND) ON A
BALUN IS RECOMMENDED IN ORDER TO AVOID UNWANTED REFLECTIONS.
Figure 3. Single-Ended to Differential Conversion Using a Balun
tude) to +10dBm (2V_P-P clock signal amplitude). The
MAX105 dynamic performance specifications are
determined by a single-ended clock drive of -2dBm
(500mVp-p clock signal amplitude). To avoid saturation
of the input amplifier stage, limit the clock power level
to a maximum of +10dBm.
Differential Clock (Sine-Wave Drive)
The advantages of differential clock drive (Figure 5)
can be obtained by using an appropriate balun or
transformer to convert single-ended sine-wave sources
into differential drives. Refer to Single-Ended Clock
Inputs (Sine-Wave Drive) for proper input amplitude
requirements.
50Ω TRANSMISSION LINES
50Ω
TO 50Ω-TERMINATED
SIGNAL SOURCE
OR BALUM
100pF
AGND
100pF
50Ω
AGND
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
and are internally buffered with a preamplifier to ensure
proper operation of the converter even with small-
amplitude sine-wave sources. The MAX105 was
designed for single-ended, low-phase noise sine wave
clock signals with as little as 500mV_P-P amplitude
(-2dBm).
Single-Ended Clock (Sine-Wave Drive)
Excellent performance is obtained by AC- or DC-cou-
pling a low-phase noise sine-wave source into a single
clock input (Figure 4). Essentially, the dynamic perfor-
mance of the converter is unaffected by clock-drive
power levels from -2dBm (500mV_p-p clock signal ampli-
50Ω
FROM SIGNAL SOURCE
100pF
AGND
100pF
CLK+,
INI+,
INQ+
CLK-,
INI-,
INQ-
AGND
Figure 4. Single-Ended Clock Input With AC-Coupled Input
Drive (CLK, INI, INQ)
Figure 5. Differential AC-Coupled Input Drive (CLK, INI, INQ)
LVDS, ECL and PECL Clock
The innovative input architecture of the MAX105 clock
also allows these inputs to be driven by LVDS-, ECL-, or
PECL-compatible input levels, ranging from 500mV_p-p
to 2V_p-p (Figure 6).
50Ω TRANSMISSION LINES
SIGNAL
SOURCE
INPUT
100pF
100Ω
100pF
LVDS LINE DRIVER
CLK-,
INI-,
INQ-
CLK+,
INI+,
INQ+
Figure 6. LVDS Input Drive (CLK, INI, INQ)
Timing Requirements
The MAX105 features a 6:12 demultiplexer, which
reduces the output data rate (including DREADY and
DOR signals) to one-half of the sample clock rate. The
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