MAX105 Datasheet, PDF (1/21 Pages) Maxim Integrated Products – Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

19-2006; Rev 0; 5/01
Dual, 6-Bit, 800Msps ADC with On-Chip,
Wideband Input Amplifier
General Description
The MAX105 is a dual, 6-bit, analog-to-digital converter
(ADC) designed to allow fast and precise digitizing of
in-phase (I) and quadrature (Q) baseband signals. The
MAX105 converts the analog signals of both I and Q
components to digital outputs at 800Msps while achiev-
ing a signal-to-noise ratio (SNR) of typically 37dB with
an input frequency of 200MHz, and an integral nonlin-
earity (INL) and differential nonlinearity (DNL) of ±0.25
LSB. The MAX105 analog input preamplifiers feature a
400MHz, -0.5dB, and a 1.5GHz, -3dB analog input
bandwidth. Matching channel-to-channel performance
is typically 0.04dB gain, 0.1LSB offset, and 0.2 degrees
phase. Dynamic performance is 36.4dB signal-to-noise
plus distortion (SINAD) with a 200MHz analog input sig-
nal and a sampling speed of 800MHz. A fully differen-
tial comparator design and encoding circuits reduce
out-of-sequence errors, and ensure excellent
metastable performance of only one error per 10¹⁶ clock
cycles.
In addition, the MAX105 provides LVDS digital outputs
with an internal 6:12 demultiplexer that reduces the out-
put data rate to one-half the sample clock rate. Data is
output in two’s complement format. The MAX105 oper-
ates from a +5V analog supply and the LVDS output
ports operate at +3.3V. The data converter’s typical
power dissipation is 2.6W. The device is packaged in
an 80-pin, TQFP package with exposed paddle, and is
specified for the extended (-40°C to +85°C) tempera-
ture range. For a lower-speed, 400Msps version of the
MAX105, please refer to the MAX107 data sheet.
Features
o Two Matched 6-Bit, 800Msps ADCs
o Excellent Dynamic Performance
36.4dB SINAD at f_IN ≈ 200MHz and
f_CLK ≈ 800MHz
o Typical INL and DNL: ±0.25LSB
o Channel-to-Channel Phase Matching: ±0.2°
o Channel-to-Channel Gain Matching: ±0.04dB
o 6:12 Demultiplexer reduces the Data Rates to
400MHz
o Low Error Rate: 10¹⁶ Metastable States at
800Msps
o LVDS Digital Outputs in Two’s Complement
Format
PART
MAX105ECS
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
80-Pin TQFP-EP
Block Diagram
VSAT Receivers
WLANs
Test Instrumentation
Communications Systems
Applications
I ADC
I
PRIMARY
PORT
I
AUXILIARY
PORT
MAX107
REF
Pin Configuration appears at end of data sheet.
Q ADC
Q
PRIMARY
PORT
Q
AUXILIARY
PORT
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