MAX1032_11 Datasheet, PDF (5/32 Pages) Maxim Integrated Products – 8- and 4-Channel, ±3 x VREF Multirange Inputs, Serial 14-Bit ADCs

8- and 4-Channel, ±3 x V_REF
Multirange Inputs, Serial 14-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD1 = V_AVDD2 = V_DVDD = V_DVDD0 = 5V, V_AGND1 = V_DGND = V_DGNDO = V_AGND2 = V_AGND3 = 0V, f_CLK = 3.5MHz (50% duty
cycle), external clock mode, V_REF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±3 x V_REF), C_DOUT = 50pF, C_SSTRB = 50pF, T_A = -40°C to +85°C, unless otherwise noted. Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS (AVDD1 and AGND1, AVDD2 and AGND2, DVDD and DGND, DVDDO and DGNDO)
Analog Supply Voltage
AVDD1
4.75
5.25
V
Digital Supply Voltage
DVDD
4.75
5.25
V
Preamplifier Supply Voltage
AVDD2
4.75
5.25
V
Digital I/O Supply Voltage
DVDDO
2.70
5.25
V
AVDD1 Supply Current
I_AVDD1
External clock mode,
external acquisition
mode, or internal
clock mode
Internal reference
External reference
3
3.5
mA
2.3
3
DVDD Supply Current
I_DVDD
External clock mode, external acquisition
mode, or internal clock mode
0.8
2
mA
AVDD2 Supply Current
I_AVDD2
External clock mode, external acquisition
mode, or internal clock mode
13.5
20
mA
DVDDO Supply Current
I_DVDDO
External clock mode, external acquisition
mode, or internal clock mode
0.01
1
mA
Total Supply Current
Partial power-down mode
Full power-down mode
Power-Supply Rejection Ratio
PSRR All analog input ranges
TIMING CHARACTERISTICS (Figures 15 and 16)
External clock mode
SCLK Period
t_CP
External acquisition mode
Internal clock mode
External clock mode
SCLK High Pulse Width (Note 6)
t_CH
External acquisition mode
Internal clock mode
External clock mode
SCLK Low Pulse Width (Note 6)
t_CL
External acquisition mode
Internal clock mode
DIN to SCLK Setup
t_DS
DIN to SCLK Hold
SCLK Fall to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Fall to SCLK Rise Setup
CS High Minimum Pulse Width
SCLK Fall to CS Rise Hold
SSTRB Rise to CS Fall Setup
t_DH
t_DO
t_DV
t_TR
t_CSS
t_CSPW
t_CSH
(Note 4)
DOUT Rise/Fall Time
C_L = 50pF
SSTRB Rise/Fall Time
C_L = 50pF
1.3
mA
0.5
µA
±0.125
LSB
0.272
62
0.228
62
µs
0.1
109
92
ns
40
109
92
ns
40
40
ns
0
ns
40
ns
40
ns
40
ns
40
ns
40
ns
0
ns
40
ns
10
ns
10
ns
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