MAX16065 Datasheet, PDF(48/61 Page) Maxim Integrated Products – 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers

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12-Channel/8-Channel, Flash-Configurable System

Managers with Nonvolatile Fault Registers

exit1-IR state. If TMS is low on the rising edge of TCK, the

controller enters the shift-IR state.

Shift-IR: In this state, the shift register in the instruction

one stage for every rising edge of TCK toward the TDO

serial output while TMS is low. The parallel outputs of

the instruction register as well as all test data registers

remain at the previous states. A rising edge on TCK with

TMS high moves the controller to the exit1-IR state. A

rising edge on TCK with TMS low keeps the controller in

the shift-IR state while moving data one stage through

the instruction shift register.

Exit1-IR: A rising edge on TCK with TMS low puts the

controller in the pause-IR state. If TMS is high on the

rising edge of TCK, the controller enters the update-IR

state.

Pause-IR: Shifting of the instruction shift register halts

temporarily. With TMS high, a rising edge on TCK puts

the controller in the exit2-IR state. The controller remains

in the pause-IR state if TMS is low during a rising edge

on TCK.

Exit2-IR: A rising edge on TCK with TMS high puts the

controller in the update-IR state. The controller loops

back to shift-IR if TMS is low during a rising edge of TCK

in this state.

Update-IR: The instruction code that has been shifted

into the instruction shift register latches to the parallel

outputs of the instruction register on the falling edge of

TCK as the controller enters this state. Once latched,

this instruction becomes the current instruction. A rising

edge on TCK with TMS low puts the controller in the run-

test/idle state. With TMS high, the controller enters the

select-DR-scan state.

Instruction Register

The instruction register contains a shift register as well

as a latched 5-bit wide parallel output. When the TAP

controller enters the shift-IR state, the instruction shift

shift-IR state, a rising edge on TCK with TMS low shifts

the data one stage toward the serial output at TDO. A

rising edge on TCK in the exit1-IR state or the exit2-IR

state with TMS high moves the controller to the update-IR

state. The falling edge of that same TCK latches the data

in the instruction shift register to the instruction register

parallel output. Table 30 shows the instructions sup-

ported by the MAX16065/MAX16066 and the respective

operational binary codes.

BYPASS: When the BYPASS instruction is latched into

the instruction register, TDI connects to TDO through the

1-bit bypass test data register. This allows data to pass

from TDI to TDO without affecting the deviceâs operation.

IDCODE: When the IDCODE instruction is latched into

the parallel instruction register, the identification data

loaded into the identification data register on the rising

edge of TCK following entry into the capture-DR state.

Shift-DR can be used to shift the identification code out

serially through TDO. During test-logic-reset, the IDCODE

instruction is forced into the instruction register. The iden-

tification code always has a â1â in the LSB position. The

next 11 bits identify the manufacturerâs JEDEC number

and number of continuation bytes followed by 16 bits for

the device and 4 bits for the version. See Table 31.

USERCODE: When the USERCODE instruction latches

into the parallel instruction register, the user-code data

user-code data register on the rising edge of TCK fol-

lowing entry into the capture-DR state. Shift-DR can be

used to shift the user-code out serially through TDO. See

Table 32. This instruction can be used to help identify

multiple MAX16065/MAX16066 devices connected in a

JTAG chain.

LOAD ADDRESS: This is an extension to the standard

IEEE 1149.1 instruction set to support access to the

memory in the MAX16065/MAX16066. When the LOAD

ADDRESS instruction latches into the instruction register,

TDI connects to TDO through the 8-bit memory address

test data register during the shift-DR state.

READ DATA: This is an extension to the standard IEEE

1149.1 instruction set to support access to the memory

in the MAX16065/MAX16066. When the READ instruction

latches into the instruction register, TDI connects to TDO

through the 8-bit memory read test data register during

the shift-DR state.

WRITE DATA: This is an extension to the standard IEEE

1149.1 instruction set to support access to the memory

in the MAX16065/MAX16066. When the WRITE instruc-

tion latches into the instruction register, TDI connects to

TDO through the 8-bit memory write test data register

during the shift-DR state.

REBOOT: This is an extension to the standard IEEE

1149.1 instruction set to initiate a software-controlled

reset to the MAX16065/MAX16066. When the REBOOT

instruction latches into the instruction register, the

MAX16065/MAX16066 resets and immediately begins

the boot-up sequence.

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