MAX16065 Datasheet, PDF (34/61 Pages) Maxim Integrated Products – 12-Channel/8-Channel, Flash-Configurable System Managers with Nonvolatile Fault Registers

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table 21. EN_OUT1–EN_OUT12 Configuration (continued)
REGISTER ADDRESS FLASH ADDRESS
33h
233h
BIT RANGE
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
DESCRIPTION
EN_OUT1 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT2 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT3 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT4 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT5 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT6 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT7 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT8 Charge-Pump Output Configuration:
0 = Charge-pump output disabled
1 = Charge-pump output enabled (active-high)
EN_OUT_s as GPIO_ (MAX16065 Only)
EN_OUT9 to EN_OUT12 can be configured as GPIO_
by setting the sequencing slot assignments in r88h
and r89h to ‘1101’ and ‘1110’, see Tables 5 and 6. If an
EN_OUT_ is configured as a general-purpose input, the
state of the pin can be read from r1Fh (see Table 22). If
an EN_OUT_ is configured as a general-purpose output,
it is controlled by r34h.
EN_OUT_ State During Power-Up
When VCC is ramped from 0 to the operating supply volt-
age, the EN_OUT_ output is high impedance until VCC
reaches UVLO and then EN_OUT_ goes into the config-
ured deasserted state after the boot-up relay. See Figures
6 and 7. Configure RESET as an active-low push-pull or
open-drain output pulled up to VCC through a 10kI resistor
for Figures 6 and 7.
Reset Output
The reset output, RESET, indicates the status of the pri-
mary sequence. It asserts during power-up/power-down
and deasserts following the reset timeout period once
the power-up sequence is complete. The power-up
sequence is complete when any MON_ inputs assigned
to the final slot exceed the undervoltage thresholds and
final sequence delay expires. When no MON_ inputs
are assigned to the final slot, the power-up sequence is
complete after the slot sequence delay expires.
During normal monitoring, RESET can be configured to
assert when any combination of MON_ inputs violates
configurable combinations of thresholds: undervoltage,
overvoltage, or early warning. Select the combination of
thresholds using r3Bh[1:0], and select the combination
of MON_ inputs using r3Ch[7:1] and r3Dh[4:0]. Note
that MON_ inputs configured as critical faults will always
cause RESET to assert regardless of these configuration bits.
RESET can be configured as push-pull or open drain
using r3Bh[3], and active-high or active-low using
r3Bh[2]. Select the reset timeout by loading a value from
Table 23 into r3Bh[7:4]. RESET can be forced to assert
by writing a ‘1’ into r3Ch[0]. RESET remains asserted
for the reset timeout period after a ‘0’ is written into
r3Ch[0]. See Table 23. The current state of RESET can
be checked by reading r20h[0].
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