MAX1224_09 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs

1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
TIMING CHARACTERISTICS
(V_DD = +2.7V to +3.6V, V_L = V_DD, V_REF = 2.048V, f_SCLK = 24.0MHz, 50% duty cycle, T_A = -40°C to +85°C, unless otherwise noted.
Typical values are at V_DD = 3V and T_A = +25°C.)
PARAMETER
SCLK Pulse-Width High
SYMBOL
t_CH
CONDITIONS
V_L = 2.7V to V_DD
V_L = 1.8V to V_DD, minimum recommended
(Note 7)
MIN
18.7
TYP MAX UNITS
ns
22.5
SCLK Pulse-Width Low
V_L = 2.7V to V_DD
18.7
t_CL
V_L = 1.8V to V_DD, minimum recommended
(Note 7)
22.5
ns
SCLK Rise to DOUT Transition
t_DOUT
C_L = 30pF, V_L = 2.7V to V_DD
C_L = 30pF, V_L = 1.8V to V_DD
17
ns
24
DOUT Remains Valid After SCLK t_DHOLD V_L = 1.8V to V_DD
4
ns
CNVST Fall to SCLK Fall
t_SETUP V_L = 1.8V to V_DD
10
ns
CNVST Pulse Width
t_CSW V_L = 1.8V to V_DD
20
ns
Power-Up Time; Full Power-Down t_PWR-UP
2
ms
Restart Time; Partial Power-Down
t_RCV
16
Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: No missing codes over temperature.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period.
Note 4: At sample rates below 10ksps, the input full-linear bandwidth is reduced to 5kHz.
Note 5: The listed value of three SCLK cycles is given for full-speed continuous conversions. Acquisition time begins on the 14th ris-
ing edge of SCLK and terminates on the next falling edge of CNST. The IC idles in acquisition mode between conversions.
Note 6: Undersampling at the maximum signal bandwidth requires the minimum jitter spec for SINAD performance.
Note 7: 1.5Msps operation guaranteed for V_L > 2.7V. See the Typical Operating Characteristics section for recommended sampling
speeds for V_L < 2.7V.
Note 8: Digital supply current is measured with the V_IH level equal to V_L, and the V_IL level equal to GND.
CNVST
t_CSW
t_SETUP
t_{CL tCH}
SCLK
DOUT
t_DHOLD
t_DOUT
Figure 1. Detailed Serial-Interface Timing
V_L
DOUT
6kΩ
DOUT
6kΩ
C_L
GND
a) HIGH-Z TO V_OH, V_OL TO V_OH,
AND V_OH TO HIGH-Z
C_L
GND
b) HIGH-Z TO V_OL, V_OH TO V_OL,
AND V_OL TO HIGH-Z
Figure 2. Load Circuits for Enable/Disable Times
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