MAX1224_09 Datasheet, PDF (15/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs

1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
The SPC register should be written as follows:
TXM = 0, external frame sync
MCM = 0, CLKX is taken from the CLKX pin
FSM = 1, burst mode
FO = 0, data transmitted/received as 16-bit words
This setup allows continuous conversion, provided that
the DRR is serviced before the next conversion.
Alternatively, autobuffering can be enabled when using
the buffered serial port to read the data without CPU
V_L
MAX1224 _SCLK
MAX1225
CNVST
DOUT
DV_DD
CLKX ^TMS320C54_
CLKR
FSX
FSR
DR
Figure 15. Interfacing to the TMS320C54_ Internal Clocks
V_L
MAX1224
MAX1225 SCLK
CNVST
DOUT
DV_DD
TMS320C54_
CLKR
FSR
DR
CLOCK
CONVERT
Figure 16. Interfacing to the TMS320C54_ External Clocks
intervention. Connect the V_L pin to the TMS320C54_
supply voltage when the MAX1224/MAX1225 are oper-
ating with an analog supply voltage higher than the
DSP supply voltage.
The MAX1224/MAX1225 can also be connected to the
TMS320C54_ by using the data transmit (DX) pin to
drive CNVST and the CLKX generated internally to
drive SCLK. A pullup resistor is required on the CNVST
signal to keep it high when DX goes high impedance
and 0001hex should be written to the DXR continuously
for continuous conversions. The power-down modes
may be entered by writing 00FFhex to the DXR (see
Figures 17 and 18).
DSP Interface to the ADSP21_ _ _
The MAX1224/MAX1225 can be directly connected to
the ADSP21_ _ _ family of DSPs from Analog Devices,
Inc. Figure 19 shows the direct connection of the
MAX1224/MAX1225 to the ADSP21_ _ _. There are two
modes of operation that can be programmed to interface
with the MAX1224/MAX1225. For continuous conver-
sions, idle CNVST low and pulse it high for one clock
cycle during the LSB of the previous transmitted word.
The ADSP21_ _ _ STCTL and SRCTL registers should be
configured for early framing (LAFR = 0) and for an
active-high frame (LTFS = 0, LRFS = 0) signal. In this
mode, the data-independent frame-sync bit (DITFS = 1)
can be selected to eliminate the need for writing to the
transmit-data register more than once. For single conver-
sions, idle CNVST high and pulse it low for the entire
conversion. The ADSP21_ _ _ STCTL and SRCTL regis-
ters should be configured for late framing (LAFR = 1)
and for an active-low frame (LTFS = 1, LRFS = 1) signal.
This is also the best way to enter the power-down modes
by setting the word length to 8 bits (SLEN = 1001).
Connect the V_L pin to the ADSP21_ _ _ supply voltage
when the MAX1224/MAX1225 are operating with a sup-
ply voltage higher than the DSP supply voltage (see
Figures 17 and 18).
CNVST
SCLK
1
1
DOUT
D0
0
0
0
0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
Figure 17. DSP Interface—Continuous Conversion
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