MAX1224_09 Datasheet, PDF (11/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 12-Bit ADCs

1.5Msps, Single-Supply, Low-Power,
True-Differential, 12-Bit ADCs
Partial Power-Down and
Full Power-Down Modes
Power consumption can be reduced significantly by plac-
ing the MAX1224/MAX1225 in either partial power-down
mode or full power-down mode. Partial power-down
mode is ideal for infrequent data sampling and fast wake-
up time applications. Pull CNVST high after the 3rd SCLK
rising edge and before the 14th SCLK rising edge to
enter and stay in partial power-down mode (see Figure
6). This reduces the supply current to 1mA. Drive CNVST
low and allow at least 14 SCLK cycles to elapse before
driving CNVST high to exit partial power-down mode.
Full power-down mode is ideal for infrequent data sam-
pling and very low supply-current applications. The
MAX1224/MAX1225 have to be in partial power-down
mode in order to enter full power-down mode. Perform
the SCLK/CNVST sequence described above to enter
partial power-down mode. Then repeat the same
sequence to enter full power-down mode (see Figure
7). Drive CNVST low, and allow at least 14 SCLK cycles
to elapse before driving CNVST high to exit full power-
down mode. In partial/full power-down mode, maintain
a logic low or a logic high on SCLK to minimize power
consumption.
Transfer Function
Figure 8 shows the unipolar transfer function for the
MAX1224. Figure 9 shows the bipolar transfer function for
the MAX1225. The MAX1224 output is straight binary,
while the MAX1225 output is two’s complement.
Applications Information
External Reference
An external reference is required for the MAX1224/
MAX1225. Use a 4.7µF and 0.01µF bypass capacitor on
the REF pin for best performance. The reference input
structure allows a voltage range of +1V to V_DD.
How to Start a Conversion
An analog-to-digital conversion is initiated by CNVST and
clocked by SCLK, and the resulting data is clocked out
on DOUT by SCLK. With SCLK idling high or low, a falling
edge on CNVST begins a conversion. This causes the
analog input stage to transition from track to hold mode,
and for DOUT to transition from high impedance to being
actively driven low. A total of 16 SCLK cycles are required
to complete a normal conversion. If CNVST is low during
the 16th falling SCLK edge, DOUT returns to high imped-
ance on the next rising edge of CNVST or SCLK,
enabling the serial interface to be shared by multiple
devices. If CNVST returns high after the 14th, but before
the 16th SCLK rising edge, DOUT remains active so con-
tinuous conversions can be sustained. The highest
throughput is achieved when performing continuous con-
versions. Figure 10 illustrates a conversion using a typical
serial interface.
CNVST
SCLK
DOUT
MODE
FIRST 8-BIT TRANSFER
EXECUTE PARTIAL POWER-DOWN TWICE
SECOND 8-BIT TRANSFER
1ST SCLK RISING EDGE
1ST SCLK RISING EDGE
0
0
0 D11 D10 D9 D8 D7
DOUT ENTERS TRI-STATE ONCE CNVST GOES HIGH
0
0
0
0
0
0
0
0
NORMAL
PPD
RECOVERY
FPD
Figure 7. SPI Interface—Full Power-Down Mode
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