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MAX1183 Datasheet, PDF (4/18 Pages) Maxim Integrated Products – Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs
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Dual 10-Bit, 40Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +3V, OVDD = +2.5V, 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through
a 10kΩ resistor, VIN = 2Vp-p (differential with respect to COM), CL = 10pF at digital outputs (Note 5), fCLK = 40MHz, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B)
Input High Threshold
CLK
VIH
PD, OE, SLEEP, T/B
0.8 x
VDD
V
0.8 x
OVDD
Input Low Threshold
CLK
VIL
PD, OE, SLEEP, T/B
0.2 x
VDD
V
0.2 x
OVDD
Input Hysteresis
VHYST
Input Leakage
IIH
IIL
Input Capacitance
CIN
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
VIH = OVDD or VDD (CLK)
VIL = 0
0.1
V
±5
µA
±5
5
pF
Output Voltage Low
VOL
ISINK = -200µA
0.2
V
Output Voltage High
VOH
ISOURCE = 200µA
OVDD
- 0.2
V
Three-State Leakage Current
ILEAK OE = OVDD
±10
µA
Three-State Leakage
Capacitance
COUT OE = OVDD
5
pF
POWER REQUIREMENTS
Analog Supply Voltage Range
Output Supply Voltage Range
Analog Supply Current
VDD
OVDD
IVDD
Operating, fINA or B = 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
2.7
3
3.6
V
1.7
2.5
3.6
V
40
60
mA
2.8
1
15
µA
Output Supply Current
Power Dissipation
IOVDD
PDISS
Operating, CL = 15pF,
fINA or B = 20MHz at -0.5dB FS
Sleep mode
Shutdown, clock idle, PD = OE = OVDD
Operating, fINA or B = 20MHz at -0.5dB FS
Sleep mode
5.8
mA
100
µA
2
10
120
180
mW
8.4
Power-Supply Rejection
PSRR
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
3
45
µW
±0.2
mV/V
±0.1
%V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
Output Enable Time
Output Disable Time
tDO
tENABLE
tDISABLE
Figure 3 (Note 3)
Figure 4
Figure 4
5
8
ns
10
ns
1.5
ns
4 _______________________________________________________________________________________
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