MAX1183 Datasheet, PDF (15/18 Pages) Maxim Integrated Products – Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 40Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
25Ω
22pF
0.1µF
V_IN
1 T1 6
N.C. ²
5
2.2µF
3
4
MINICIRCUITS
TT1–6
25Ω
0.1µF
22pF
25Ω
22pF
0.1µF
V_IN
1 T1 6
N.C. ²
5
2.2µF
3
4
MINICIRCUITS
TT1–6
25Ω
0.1µF
22pF
INA+
COM
INA-
MAX1183
INB+
INB-
REFP
VIN
0.1µF
1kΩ _RISO
50Ω
MAX4108
100Ω
1kΩ
REFN _0.1µF
100Ω
REFP
VIN
0.1µF
1kΩ RISO
50Ω
MAX4108
100Ω
1kΩ
REFN _0.1µF
100Ω
CIN
22pF
RISO
50Ω
CIN
22pF
CIN
22pF
RISO
50Ω
CIN
22pF
INA+
COM
INA-
MAX1183
INB+
INB-
Figure 7. Using an Op Amp for Single-Ended, AC-Coupled
Input Drive
Figure 6. Transformer-Coupled Input Drive
quadrature (Q) carrier component, where the Q compo-
nent is 90-degree phase-shifted with respect to the in-
phase component. At the receiver, the QAM signal is
divided down into its I and Q components, essentially
representing the modulation process reversed. Figure 8
displays the demodulation process performed in the
analog domain, using the dual matched +3V, 10-bit
ADC MAX1183 and the MAX2451 quadrature demodu-
lator to recover and digitize the I and Q baseband sig-
nals. Before being digitized by the MAX1183, the
mixed-down signal components may be filtered by
matched analog filters, such as Nyquist or pulse-shap-
ing filters, which remove any unwanted images from the
mixing process, thereby enhancing the overall SNR
performance and minimizing intersymbol interference.
Grounding, Bypassing, and
Board Layout
The MAX1183 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass V_DD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OV_DD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider the
use of a split ground plane arranged to match the
physical location of the analog ground (GND) and the
digital output driver ground (OGND) on the ADC’s
package. The two ground planes should be joined at a
single point such that the noisy digital ground currents
do not interfere with the analog ground plane. The ideal
location of this connection can be determined experi-
mentally at a point along the gap between the two
ground planes, which produces optimum results. Make
this connection with a low-value, surface-mount resistor
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