MAX1183 Datasheet, PDF (12/18 Pages) Maxim Integrated Products – Dual 10-Bit, 40Msps, +3V, Low-Power ADC with Internal Reference and Parallel Outputs

Dual 10-Bit, 40Msps, +3V, Low-Power ADC with
Internal Reference and Parallel Outputs
SNR_dB = 20 ✕ log₁₀ (1 / [2π ✕ f_IN ✕ t_AJ])
where f_IN represents the analog input frequency and
t_AJ is the time of the aperture jitter.
Clock jitter is especially critical for undersampling
applications. The clock input should always be consid-
ered as an analog input and routed away from any ana-
log input or other digital signal lines.
The MAX1183 clock input operates with a voltage thresh-
old set to V_DD/2. Clock inputs with a duty cycle other
than 50% must meet the specifications for high and low
periods as stated in the Electrical Characteristics.
System Timing Requirements
Figure 3 depicts the relationship between the clock
input, analog input, and data output. The MAX1183
samples at the rising edge of the input clock. Output
data for channels A and B is valid on the next rising
edge of the input clock. The output data has an internal
latency of five clock cycles. Figure 4 also determines
the relationship between the input clock parameters
and the valid output data on channels A and B.
Digital Output Data, Output Data Format
Selection (T/B), Output Enable (OE)
All digital outputs, D0A–D9A (Channel A) and
D0B–D9B (Channel B) are TTL/CMOS-logic compati-
ble. There is a five-clock-cycle latency between any
particular sample and its corresponding output data.
The output coding can be chosen to be either straight
offset binary or two’s complement (Table 1) controlled
by a single pin (T/B). Pull T/B low to select offset binary
and high to activate two’s complement output coding.
The capacitive load on the digital outputs D0A–D9A
and D0B–D9B should be kept as low as possible
(<15pF) to avoid large digital currents that could feed
back into the analog portion of the MAX1183, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1183
small series resistors (e.g., 100Ω) may be added to the
digital output paths, close to the MAX1183.
ANALOG INPUT
5-CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
CLOCK INPUT
DATA OUTPUT
D9A–D0A
DATA OUTPUT
D9B–D0B
t_DO
t_CH
t_CL
N-6
N-5
N-4
N-3
N-2
N-1
N-6
N-5
N-4
N-3
N-2
N-1
N
N+1
N
N+1
Figure 3. System Timing Diagram
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