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MAX11646 Datasheet, PDF (4/20 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
POWER REQUIREMENTS
Power-Supply Rejection Ratio
PSRR Full-scale input (Note 9)
±0.01 ±0.5 LSB/V
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11647), VDD = 4.5V to 5.5V (MAX11646), VREF = 2.048V (MAX11647), VREF = 4.096V (MAX11646), fSCL =
1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
Bus Free Time Between a
STOP (P) and a
START (S) Condition
tBUF
400
kHz
1.3
μs
Hold Time for a START (S)
Condition
tHD:STA
0.6
μs
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a REPEATED
START Condition (Sr)
tLOW
tHIGH
tSU:STA
1.3
μs
0.6
μs
0.6
μs
Data Hold Time
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
tHD:DAT
tSU:DAT
tR
(Note 10)
Measured from 0.3VDD to 0.7VDD
0
100
20 +
0.1CB
900
ns
ns
300
ns
Fall Time of SDA Transmitting
20 +
tF
Measured from 0.3VDD to 0.7VDD (Note 11) 0.1CB
300
ns
Setup Time for a STOP (P)
Condition
tSU:STO
0.6
μs
Capacitive Load for Each Bus Line
CB
Pulse Width of Spike Suppressed
tSP
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12)
Serial-Clock Frequency
fSCLH (Note 13)
Hold Time, REPEATED START
Condition (Sr)
tHD:STA
400
pF
50
ns
1.7
MHz
160
ns
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a REPEATED
START Condition (Sr)
tLOW
tHIGH
tSU:STA
320
ns
120
ns
160
ns
Data Hold Time
Data Setup Time
tHD:DAT
tSU:DAT
(Note 10)
0
150
ns
10
ns
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