MAX11646 Datasheet, PDF (15/20 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 10-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
Internal Clock
When configured for internal clock mode (CLK = 0), the
MAX11646/MAX11647 use their internal oscillator as
the conversion clock. In internal clock mode, the
MAX11646/MAX11647 begin tracking the analog input
after a valid address on the eighth rising edge of the
clock. On the falling edge of the ninth clock, the analog
signal is acquired and the conversion begins. While
converting the analog input signal, the MAX11646/
MAX11647 hold SCL low (clock stretching). After the
conversion completes, the results are stored in internal
memory. If the scan mode is set for multiple conver-
sions, they all happen in succession with each addi-
tional result stored in memory. The MAX11646/
MAX11647 contain two 10-bit blocks of memory. Once
all conversions are complete, the MAX11646/MAX11647
release SCL, allowing it to be pulled high. The master can
now clock the results out of the memory in the same
order the scan conversion has been done at a clock
rate of up to 1.7MHz. SCL is stretched for a maximum
of 7.6µs per channel (see Figure 10).
The device memory contains all of the conversion results
when the MAX11646/MAX11647 release SCL. The con-
verted results are read back in a first-in/first-out (FIFO)
sequence. The memory contents can be read continu-
ously. If reading continues past the result stored in
memory, the pointer wraps around and point to the first
result. Note that only the current conversion results are
read from memory. The device must be addressed with
a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal, reducing the system noise during con-
version. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
11
S SLAVE ADDRESS R A CLOCK STRETCH
tACQ
tCONV
8
RESULT 2 MSBs A
8
RESULT 8 LSBs
11
A P or Sr
NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
11
S SLAVE ADDRESS R A
CLOCK STRETCH
tACQ1
tCONV1
tACQ2
tCONV2
8
1
8
1
CLOCK STRETCH RESULT 1 ( 2MSBs) A RESULT 1 (8 LSBs) A
tACQN
tCONVN
8
1
8
11
RESULT N (8MSBs) A RESULT N (8LSBs) A P or Sr
NUMBER OF BITS
Figure 10. Internal Clock Mode Read Cycles
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