MAX11646 Datasheet, PDF (16/20 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 1-/2-Channel, 2-Wire Serial, 10-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
1-/2-Channel, 2-Wire Serial, 10-Bit ADCs
External Clock
When configured for external clock mode (CLK = 1),
the MAX11646/MAX11647 use the SCL as the conver-
sion clock. In external clock mode, the MAX11646/
MAX11647 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
converted data is available immediately after the first
four empty high bits. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to re-address the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX11646/MAX11647 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. The scanned results are written to mem-
ory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission, the first byte
begins with six empty bits during which SDA is left
high. Each byte has to be acknowledged by the master
or the memory transmission is terminated. It is not pos-
sible to read the memory independently of conversion.
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
11
8
1
8
S SLAVE ADDRESS R A RESULT (2 MSBs) A RESULT (8 LSBs)
11
A P OR Sr
t_ACQ
t_CONV
NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
11
8
1
8
1
S _{SLAVE ADDRESS} R A _{RESULT 1 (2 MSBs)} A _{RESULT 2 (8 LSBs)} A
t_ACQ1
t_CONV1
t_ACQ2
8
1
8
11
RESULT N (2 MSBs) ^A RESULT N (8 LSBs) ^{A P OR Sr}
t_ACQN
t_CONVN
NUMBER OF BITS
Figure 11. External Clock Mode Read Cycle
Table 5. Scanning Configuration
SCAN1
0
0
1
1
SCAN0
0
1
0
1
SCANNING CONFIGURATION
Scans up from AIN0 to the input selected by CS0.
Converts the input selected by CS0 eight times (see Tables 3 and 4).*
Reserved. Do not use.
Converts input selected by CS0.*
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not acknowledge occurs.
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