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| MAX11612_11 Datasheet, PDF (4/22 Pages) Maxim Integrated Products – Low-Power, 4-/8-/12-Channel, I2C, 12-Bit ADCs in Ultra-Small Packages | |||
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Low-Power, 4-/8-/12-Channel, I2C,
12-Bit ADCs in Ultra-Small Packages
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1â5 for programming notation.) (Note 1)
PARAMETER
POWER REQUIREMENTS
Supply Voltage
Supply Current
Power-Supply Rejection Ratio
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
VDD
IDD
PSRR
MAX11613/MAX11615/MAX11617
MAX11612/MAX11614/MAX11616
fSAMPLE = 94.4ksps
external clock
Internal reference
External reference
fSAMPLE = 40ksps
internal clock
Internal reference
External reference
fSAMPLE = 10ksps
internal clock
Internal reference
External reference
fSAMPLE =1ksps
internal clock
Internal reference
External reference
Shutdown (internal REF off)
Full-scale input (Note 10)
2.7
3.6
V
4.5
5.5
900 1150
670 900
530
230
380
µA
60
330
6
0.5
10
±0.5 ±2.0 LSB/V
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), VDD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), VREF = 2.048V
(MAX11613/MAX11615/MAX11617), VREF = 4.096V (MAX11612/MAX11614/MAX11616), fSCL = 1.7MHz, TA = TMIN to TMAX, unless
otherwise noted. Typical values are at TA = +25°C, see Tables 1â5 for programming notation.) (Note 1)
PARAMETER
SYMBOL
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
fSCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
tBUF
CONDITIONS
MIN TYP MAX UNITS
400
kHz
1.3
µs
Hold Time for START (S) Condition
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated START
Condition (Sr)
Data Hold Time (Note 11)
Data Setup Time
Rise Time of Both SDA and SCL
Signals, Receiving
tHD, STA
tLOW
tHIGH
tSU, STA
tHD, DAT
tSU, DAT
tR
Measured from 0.3VDD - 0.7VDD
0.6
1.3
0.6
0.6
0
100
20 + 0.1CB
µs
µs
µs
µs
900
ns
ns
300
ns
Fall Time of SDA Transmitting
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
tF
tSU, STO
CB
tSP
Measured from 0.3VDD - 0.7VDD (Note 12)
20 + 0.1CB
0.6
300
ns
µs
400
pF
50
ns
4 _______________________________________________________________________________________
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