MAX11612_11 Datasheet, PDF (17/22 Pages) Maxim Integrated Products – Low-Power, 4-/8-/12-Channel, I2C, 12-Bit ADCs in Ultra-Small Packages

Low-Power, 4-/8-/12-Channel, I²C,
12-Bit ADCs in Ultra-Small Packages
Table 5. Scanning Configuration
SCAN1
0
0
SCAN0
0
1
SCANNING CONFIGURATION
Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 1011, the scanning
stops at AIN11. When AIN_/REF is set to be a REF input/output, scanning stops at AIN2 or AIN10.
*Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4).
MAX11612/MAX11613: Scans upper half of channels.
Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1,
and AIN2, the only scan that takes place is AIN2 (MAX11612/MAX11613). When AIN/REF is set to be a
REF input/output, scanning stops at AIN2.
MAX11614/MAX11615: Scans upper quartile of channels.
1
0
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only
scan that takes place is AIN6 (MAX11614/MAX11615).
MAX11616/MAX11617: Scans upper half of channels.
Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only
scan that takes place is AIN6 (MAX11616/MAX11617). When AIN/REF is set to be a REF input/output,
scanning stops at selected channel or AIN10.
1
1
*Converts channel selected by CS3–CS0.
*When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs
perpetually until not-acknowledge occurs.
converted data is available immediately after the first
four empty high bits. The device continuously converts
input channels dictated by the scan mode until given a
not acknowledge. There is no need to readdress the
device with a read command to obtain new conversion
results (see Figure 11).
The conversion must complete in 1ms, or droop on the
track-and-hold capacitor degrades conversion results.
Use internal clock mode if the SCL clock period
exceeds 60µs.
The MAX11612–MAX11617 must operate in external
clock mode for conversion rates from 40ksps to
94.4ksps. Below 40ksps, internal clock mode is recom-
mended due to much smaller power consumption.
Scan Mode
SCAN0 and SCAN1 of the configuration byte set the
scan mode configuration. Table 5 shows the scanning
configurations. If AIN_/REF is set to be a reference input
or output (SEL1 = 1, Table 6), AIN_/REF is excluded from
a multichannel scan. The scanned results are written to
memory in the same order as the conversion. Read the
results from memory in the order they were converted.
Each result needs a 2-byte transmission; the first byte
begins with four empty bits, during which SDA is left
high. Each byte has to be acknowledged by the master
or the memory transmission is terminated. It is not possi-
ble to read the memory independently of conversion.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2)
default to a single-ended, unipolar, single-channel con-
version on AIN0 using the internal clock with V_DD as the
reference and AIN_/REF configured as an analog input.
The memory contents are unknown after power-up.
Automatic Shutdown
Automatic shutdown occurs between conversions when
the MAX11612–MAX11617 are idle. All analog circuits
participate in automatic shutdown except the internal
reference due to its prohibitively long wake-up time.
When operating in external clock mode, a STOP, not-
acknowledge, or repeated START condition must be
issued to place the devices in idle mode and benefit
from automatic shutdown. A STOP condition is not nec-
essary in internal clock mode to benefit from automatic
shutdown because power-down occurs once all con-
version results are written to memory (Figure 10). When
using an external reference or V_DD as a reference, all
analog circuitry is inactive in shutdown and supply cur-
rent is less than 0.5µA. The digital conversion results
obtained in internal clock mode are maintained in memo-
ry during shutdown and are available for access through
the serial interface at any time prior to a STOP or a
repeated START condition.
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