MAX11612 Datasheet, PDF (4/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V_DD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V_REF = 2.048V
(MAX11613/MAX11615/MAX11617), V_REF = 4.096V (MAX11612/MAX11614/MAX11616), f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless
otherwise noted. Typical values are at T_A = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
POWER REQUIREMENTS
Supply Voltage
Supply Current
Power-Supply Rejection Ratio
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
V_DD
I_DD
PSRR
MAX11613/MAX11615/MAX11617
MAX11612/MAX11614/MAX11616
f_SAMPLE = 94.4ksps
external clock
Internal reference
External reference
f_SAMPLE = 40ksps
internal clock
Internal reference
External reference
f_SAMPLE = 10ksps
internal clock
Internal reference
External reference
f_SAMPLE =1ksps
internal clock
Internal reference
External reference
Shutdown (internal REF off)
Full-scale input (Note 9)
2.7
3.6
V
4.5
5.5
900 1150
670
900
530
230
380
µA
60
330
6
0.5
10
±0.5 ±2.0 LSB/V
TIMING CHARACTERISTICS (Figure 1)
(V_DD = 2.7V to 3.6V (MAX11613/MAX11615/MAX11617), V_DD = 4.5V to 5.5V (MAX11612/MAX11614/MAX11616), V_REF = 2.048V
(MAX11613/MAX11615/MAX11617), V_REF = 4.096V (MAX11612/MAX11614/MAX11616), f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless
otherwise noted. Typical values are at T_A = +25°C, see Tables 1–5 for programming notation.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS FOR FAST MODE
Serial-Clock Frequency
f_SCL
Bus Free Time Between a STOP (P)
and a START (S) Condition
t_BUF
Hold Time for START (S) Condition
Low Period of the SCL Clock
High Period of the SCL Clock
t_{HD, STA}
t_LOW
t_HIGH
Setup Time for a Repeated START
Condition (Sr)
t_{SU, STA}
Data Hold Time (Note 10)
Data Setup Time
t_{HD, DAT}
t_{SU, DAT}
Rise Time of Both SDA and SCL
Signals, Receiving
t_R
Measured from 0.3V_DD - 0.7V_DD
MIN TYP MAX UNITS
1.3
0.6
1.3
0.6
0.6
0
100
20 + 0.1C_B
400
kHz
µs
µs
µs
µs
µs
900
ns
ns
300
ns
Fall Time of SDA Transmitting
Setup Time for STOP (P) Condition
Capacitive Load for Each Bus Line
Pulse Width of Spike Suppressed
t_F
t_{SU, STO}
C_B
t_SP
Measured from 0.3V_DD - 0.7V_DD (Note 11)
20 + 0.1C_B
0.6
300
ns
µs
400
pF
50
ns
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