MAX11612 Datasheet, PDF (20/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital sam-
ples, the theoretical maximum SNR is the ratio of the full-
scale analog input (RMS value) to the RMS quantization
error (residual error). The ideal, theoretical minimum ana-
log-to-digital noise is caused by quantization error only
and results directly from the ADC’s resolution (N Bits):
SNR_MAX[dB] = 6.02_dB  N + 1.76_dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals.
SINAD(dB)
=
20
×
log
⎡
⎣⎢
SignalRMS
NoiseRMS + THDRMS
⎤
⎦⎥
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the
ADC’s full-scale range, calculate the ENOB as follows:
ENOB = (SINAD - 1.76)/6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
THD
=
20 ×
⎛
log
⎜
⎜
⎝
⎛
⎜
V₂₂
+
⎝
V₃₂ + V₄₂ +
V₁
V₅₂
⎞
⎟
⎠
⎞
⎟
⎟
⎠
where V₁ is the fundamental amplitude, and V₂ through
V₅ are the amplitudes of the 2nd- through 5th-order har-
monics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest distor-
tion component.
PROCESS: BiCMOS
Chip Information
Selector Guide
PART
INTERNAL SUPPLY
INPUT
CHANNELS
REFERENCE
(V)
VOLTAGE
(V)
INL
(LSB)
MAX11612
4
MAX11613
4
MAX11614
8
MAX11615
8
MAX11616
12
MAX11617
12
4.096
2.048
4.096
2.048
4.096
2.048
4.5 to 5.5 ±1
2.7 to 3.6 ±1
4.5 to 5.5 ±1
2.7 to 3.6 ±1
4.5 to 5.5 ±1
2.7 to 3.6 ±1
20 ______________________________________________________________________________________