MAX11612 Datasheet, PDF (16/22 Pages) Maxim Integrated Products – 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs

2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/8-/12-Channel, 2-Wire Serial, 12-Bit ADCs
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK
1
7
11
S SLAVE ADDRESS R A CLOCK STRETCH
tACQ
tCONV
8
RESULT 4 MSBs A
8
RESULT 8 LSBs
11
A P or Sr
NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK
1
7
11
S SLAVE ADDRESS R A
CLOCK STRETCH
tACQ1
tCONV1
tACQ2
tCONV2
8
1
8
1
CLOCK STRETCH RESULT 1 ( 4MSBs) A RESULT 1 (8 LSBs) A
tACQN
tCONVN
8
1
8
11
RESULT N (4MSBs) A RESULT N (8LSBs) A P or Sr
NUMBER OF BITS
Figure 10. Internal Clock Mode Read Cycles
The converted results are read back in a first-in-first-out
(FIFO) sequence. If AIN_/REF is set to be a reference
input or output (SEL1 = 1, Table 6), AIN_/REF is exclud-
ed from a multichannel scan. This does not apply to the
MAX11614/MAX11615 as each provides separate pins
for AIN7 and REF. The memory contents can be read
continuously. If reading continues past the result stored
in memory, the pointer wraps around and point to the
first result. Note that only the current conversion results
is read from memory. The device must be addressed
with a read command to obtain new conversion results.
The internal clock mode’s clock stretching quiets the
SCL bus signal reducing the system noise during
conversion. Using the internal clock also frees the bus
master (typically a microcontroller) from the burden of
running the conversion clock, allowing it to perform
other tasks that do not need to use the bus.
External Clock
When configured for external clock mode (CLK = 1),
the MAX11612–MAX11617 use the SCL as the conver-
sion clock. In external clock mode, the MAX11612–
MAX11617 begin tracking the analog input on the ninth
rising clock edge of a valid slave address byte. Two
SCL clock cycles later, the analog signal is acquired
and the conversion begins. Unlike internal clock mode,
MASTER TO SLAVE
SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK
1
7
11
8
1
8
S SLAVE ADDRESS R A RESULT (4 MSBs) A RESULT (8 LSBs)
11
A P OR Sr
tACQ
tCONV
NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK
1
7
11
8
1
8
1
S _{SLAVE ADDRESS} R A _{RESULT 1 (4 MSBs)} A _{RESULT 2 (8 LSBs)} A
tACQ1
tCONV1
tACQ2
Figure 11. External Clock Mode Read Cycle
8
1
8
11
RESULT N (4 MSBs) ^A RESULT N (8 LSBs) A ^{P OR Sr}
tACQN
tCONVN
NUMBER OF BITS
16 ______________________________________________________________________________________