MAX11200 Datasheet, PDF (4/27 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO

24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, single-cycle mode (SCYCLE = 1), TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
POWER REQUIREMENTS
Analog Supply
VAVDD
Digital Supply
VDVDD
Total Operating Current
AVDD + DVDD
Buffers disabled
Buffers enabled
AVDD Sleep Current
AVDD Operating Current
Buffers disabled
Buffers enabled
DVDD Sleep Current
DVDD Operating Current
SPI TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
SCLK Clock Period
tCP
SCLK Pulse-Width High
tCH
SCLK Pulse-Width Low
CS Low to 1st SCLK Rise Setup
CS High to 17th SCLK Setup
tCL
tCSS0
tCSS1
60% duty cycle at 5MHz
CS High After 16th SCLK Falling
Edge Hold
tCSH1
CS Pulse-Width High
tCSW
DIN to SCLK Setup
tDS
DIN Hold After SCLK
tDH
RDY/DOUT Transition Valid After
SCLK Fall
tDOT
Output transition time, data changes on
falling edge of SCLK
RDY/DOUT Remains Valid After
SCLK Fall
tDOH
Output hold time allows for negative edge
data read
RDY/DOUT Valid Before SCLK Rise
CS Rise to RDY/DOUT Disable
tDOL
tDOD
tDOL = tCL - tDOT
CLOAD = 20pF
CS Fall to RDY/DOUT Valid
tDOE
Default value of RDY is 1 for minimum
specification; maximum specification for
valid 0 on RDY/DOUT
MIN TYP MAX UNITS
2.7
3.6
V
1.7
3.6
V
235 300
FA
255
0.15
2
FA
185 235
FA
205
0.25
2
FA
50
65
FA
5
MHz
200
ns
80
ns
80
ns
40
ns
40
ns
3
ns
40
ns
40
ns
0
ns
40
ns
3
ns
40
ns
25
ns
0
40
ns
DATA Fetch
Maximum time after RDY asserts to read
tDF DATA register; t_CNV is the time for one
0
conversion
tCNV -
60 x tCP
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: VAINP = VAINN.
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
lower or continuous data rate of 60sps/50sps.
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