MAX11200 Datasheet, PDF (14/27 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO

24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
Serial-Digital Interface
The MAX11200/MAX11210 interface is fully compatible
with SPI-, QSPI-, and MICROWIRE-standard serial inter-
faces. The SPI interface provides access to nine on-chip
registers that are 8 or 24 bits wide.
Drive CS low to transfer data in and out of the devices.
Clock in data at DIN on the rising edge of SCLK. The
RDY/DOUT output serves two functions: conversion sta-
tus and data read. To find the conversion status, assert
CS low and read the RDY/DOUT output; the conversion
is in progress if the RDY/DOUT output reads logic-high
and the conversion is complete if the RDY/DOUT output
reads logic-low. Data at RDY/DOUT changes on the
falling edge of SCLK and is valid on the rising edge of
SCLK. DIN and DOUT are transferred MSB first. Drive
CS high to force DOUT high impedance and cause
the devices to ignore any signals on SCLK and DIN.
Connect CS low for 3-wire operation. Figures 5, 6, and 7
show the SPI timing diagrams.
tCSH0
tCSS0
CS
tDS
tDH
tCP
tCL tCH
tCSH1
tCSW
tCSS1
SCLK
0
1
8
DIN
X
HIGH-Z
RDY/DOUT
1
0
CAL1
CAL0
IMPD RATE2 RATE1 RATE0
tDOE
tDOD
HIGH-Z
Figure 5. SPI Command Byte
tCSH0
tCSS0
CS
SCLK 0
1
tDS
tDH
tCP
tCL
tCH
8
9
tCSW
tCSH1
tCSS1
16
DIN ^X
HIGH-Z
RDY/DOUT
1
1
tDOE
X RS3 RS2 RS1 RS0 W/R D7 D6 D5 D4 D3 D2 D1 D0
tDOD
HIGH-Z
Figure 6. SPI Register Access Write
CS
SCLK
tCSS0
1
tDS
tDH
tCP
tCL
tCH
tDOT
tDOH
tDO1
8
9
tDOD
tCSS1
16
DIN X
HIGH-Z
RDY/DOUT
1
1
tDOE
X
RS3 RS2 RS1 RS0 W/R
X
X
X
X
X
X
X
X
D7
D6
D5 D4
D3
D2
D1
D0
Figure 7. SPI Register Access Read
HIGH-Z
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