MAX11200 Datasheet, PDF (24/27 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with GPIO

24-Bit, Single-Channel, Ultra-Low-Power,
Delta-Sigma ADCs with GPIO
SCGC: Self-Calibration Gain Register
The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked in/
out MSB first. This register holds the self-calibration gain value. The format is always in two’s complement binary format.
A write to the self-calibration gain register is allowed. The written value remains valid until it is either rewritten or until
an on-demand self-calibration operation is performed, which overwrites the user-supplied value. Any attempt to write
to this register during an active calibration operation is ignored.
The self-calibration gain value is used to scale the self-calibration offset corrected conversion result before the system
offset and gain calibration values have been applied, provided the NOSCG bit in the CTRL3 register is set to 0. The
self-calibration gain value scales the self-calibration offset corrected conversion result by up to 2x or can correct a gain
error of approximately -50%. The gain is corrected to within 2 LSB.
Table 20. SCGC Register (Read/Write)
BIT
DEFAULT
B23
B22
B21
B20
B19
B18
B17
B16
0
0
0
0
0
0
0
0
BIT
DEFAULT
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
0
0
0
0
0
BIT
DEFAULT
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
Table 21. Data Rates for All Combinations of RATE[2:0] (LINEF = 0)
RATE[2:0]
000
001
010
011
100
101
110
111
SINGLE-CYCLE DATA RATE (sps)
1
2.5
5
10
15
30
60
120
CONTINUOUS DATA RATE (sps)
—
—
—
—
60
120
240
480
Table 22. Data Rates for All Combinations of RATE[2:0] (LINEF = 1)
RATE[2:0]
000
001
010
011
100
101
110
111
SINGLE-CYCLE DATA RATE (sps)
0.833
2.08
4.17
8.33
12.5
25
50
100
CONTINUOUS DATA RATE (sps)
—
—
—
—
50
100
200
400
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