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MAX11040K Datasheet, PDF (4/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs
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24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
DIGITAL INPUTS (SCLK, CS, DIN, SYNC, CASCIN, DRDYIN, XIN)
Input Low Voltage
VIL
Input High Voltage
VIH
Input Hysteresis
VHYS VDVDD = 3.0V
Input Leakage Current
IL
Input Capacitance
CIN
CMOS DIGITAL OUTPUTS (DOUT, CASCOUT, DRDYOUT, CLKOUT)
0.7 x
VDVDD
Output Low Voltage
VOL ISINK = 5mA
Output High Voltage
VOH ISOURCE = 1mA
Three-State Leakage Current
ILT
Three-State Capacitance
COUT
OPEN-DRAIN DIGITAL OUTPUTS (OVRFLW, FAULT)
0.85 x
VDVDD
Output Low Voltage
VOL ISINK = 5mA
Output High Voltage
Internal Pullup Resistance
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Analog Supply Current (Note 11)
VOH
AVDD
DVDD
IAVDD
Digital Supply Current (Note 11)
IDVDD
AC Positive-Supply Rejection
DC Positive-Supply Rejection
ESD PROTECTION
All Pins
ESD
TIMING CHARACTERISTICS (Figures 7–10)
SCLK Clock Period
tSCP
SCLK Pulse Width (High and Low)
tPW
DIN or CS to SCLK Fall Setup
tSU
SCLK Fall to DIN Hold
SCLK Rise to CS Rise
tHD
tCSH1
Internal pullup only
0.85 x
VDVDD
3.0
2.7
Normal operation
Shutdown and fXINCLOCK = 0Hz
Normal operation
Shutdown and fXINCLOCK = 0Hz
VAVDD = 3.3V + 100mVP-P at 1kHz
VAVDD = VDVDD = 3.0V to 3.6V
Human Body Model
50
20
10
0
0
TYP
100
±0.01
15
15
30
25
0.1
11
0.3
70
75
2.5
MAX UNITS
0.3 x
V
VDVDD
V
mV
±1
μA
pF
0.15 x
VDVDD
V
V
±1
μA
pF
0.15 x
VDVDD
V
V
kΩ
3.6
V
VAVDD
V
35
mA
5
μA
15
mA
μA
dB
dB
kV
ns
ns
ns
ns
ns
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