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MAX11040K Datasheet, PDF (28/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs
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24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
SYNC for Simultaneous
Sampling with Multiple Devices
The SYNC input permits multiple devices to sample
simultaneously. The mismatch between the power-up
reset of multiple devices causes the devices to begin
conversion at different times. After a falling edge on the
SYNC input, the device completes the current conver-
sion and then synchronizes subsequent conversions
(see Figure 16).
Upon a SYNC falling edge, the devices measure the time
between the SYNC falling edge to the preceding DRDY-
OUT falling edge, wait until the next DRDYOUT falling
edge, then pause the ADC for the measured amount of
time. Figure 16 shows an example where the converter
is regularly sampling the input and producing a DRDY-
OUT with a period tS. The effect of a SYNC falling edge
as shown in Figure 16 is described in sequence below:
1) A SYNC falling edge is issued two XIN clock cycles
after the DRDYOUT event 2.
2) The converter remembers the two XIN clock cycles,
and completes the current sample, issuing DRDYOUT
event 3 a period of tS after DRDYOUT event 2.
3) Then, the converter pauses for the remembered time
period, two XIN clock cycles for this example.
4) Correspondingly, DRDYOUT event 4 is issued two
XIN cycles later than it would have without the
SYNC falling edge.
5) The process continues as normal with DRDYOUT
event 5 appearing tS after DRDYOUT event 4.
NOTE: THE LATENCY IS NOT TO SCALE.
1
tS
AIN_
XIN
tS
2
tS
3
tS
4
tS
tS
DELAY 2
CYCLES
5
tS
tS
tS
6
tS
DRDYOUT
1
SYNC
Figure 16. Effect of a SYNC Falling Edge
2
3
MEASURE
PAUSE
4
5
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