MAX11040K Datasheet, PDF (31/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs

24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Signal Distortion at SYNC Falling Edges
Each SYNC falling edge causes a disruption in the digi-
tal filter timing proportional to the delay from the previ-
ous falling edge of DRDYOUT to the falling edge of
SYNC. Any analysis of the output data that assumes a
uniform sampling period sees an error proportional to
that delay, with a maximum value determined by the
maximum derivative of the analog input. Figure 19
shows the effect of this discontinuity at output sample 5.
Assuming a 60Hz ±2.2V sine wave, the maximum pos-
sible error on any given sample caused by a SYNC
falling edge is:
V_{ERROR_MAX} = 2.2V x 2π x 60Hz x t_{DRDYOUT_TO_SYNC}
= 0.83μV/ns x t_{DRDYOUT_TO_SYNC}
The delay from DRDYOUT to SYNC is quantized to
within one cycle of the 24.576MHz clock. SYNC pulses
that are asynchronous to DRDYOUT may cause large
errors. To eliminate this error, use a single clock source
for all devices and avoid disrupting the output data tim-
ing with SYNC pulses while making high-precision
measurements. Alternately, minimize the delay from
DRDYOUT to SYNC to minimize the error.
Example:
Assume f_{AIN_} = 60Hz, f_S = 16ksps, and eight total
devices in the chain.
Device 1 has the longest t_{DRDYOUT_TO_SYNC} delay,
therefore the worst-case SYNC error.
If device 1 has the fastest XIN clock in the chain, and
device 2 has the slowest XIN clock in the chain, and
they differ by 0.1%, device 1 completes its conversion
as much as 0.1% earlier than device 2. Hence, the
delay of device 2 is:
0.1% x (1/16kHz ) = 62.5ns
The signal then propagates down the chain at a time
delay of nominally 20ns for each device.
The total delay back to the SYNC falling edge after
going through six additional delays is:
t_DELAY = 62.5ns + 6 x 20ns = 182.5ns
Maximum % Error = 2π x f_IN x t_{DRDYOUT_TO_SYNC x}
100% ^{= 2 x π x 60Hz x 182.5ns x 100% = 0.007%}
The above error is relative to the signal level, not to the
full scale of the data converter.
t_S
1
AIN_
DRDYOUT
NOTE: THE LATENCY IS NOT TO SCALE.
t_S
2
t_S
t_S
3
t_{DRYOUT_TO_SYNC}
4
t_S
5
t_S
t_S
t_S
6
t_S
1
2
3
4
SYNC
RECONSTRUCTED
DIGITAL OUTPUT
PAUSE FOR
MEASURE
t_{DRYOUT_TO_SYNC}
t_{DRYOUT_TO_SYNC}
1
2
3
4
DISCONTINUITY DUE TO SYNC EVENT
5
6
Figure 19. Example of Discontinuity in Reconstructed Digital Output Due to SYNC Falling Edge with a Large DRDYOUT-to-SYNC Delay
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