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MAX11040K Datasheet, PDF (29/35 Pages) Maxim Integrated Products – 24-/16-Bit, 4-Channel, Simultaneous-Sampling, Cascadable, Sigma-Delta ADCs
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Referring back to the analog input, since the entire sam-
pling section of the converter also paused for two clock
cycles, the sampling point for sample 5 is also paused
by two clock cycles, possibly creating a small distur-
bance at the SYNC falling edge. This disturbance is fil-
tered with the digital filter, which makes it less distinct.
If the SYNC falling edge occurred during the same XIN
clock period as the DRDYOUT signal, the disturbance
does not affect the periodic timing since the SYNC
falling edge would demand a pause of zero XIN clock
cycles. Hence, connecting the DRDYOUT of one con-
verter to the SYNC inputs of many converters, as illus-
trated in Figure 13, aligns the sampling of the
converters on the first SYNC falling edge, but does not
disturb a regular sampling process for future samples.
See the Multiple Device Synchronization section for dif-
ferent ways to use the SYNC input.
Transfer Function
Figures 17 shows the bipolar I/O transfer function.
Code transitions occur halfway between successive-
integer LSB values. Output coding is binary, with 1 LSB
= (0.88 x VREFIO) x 2/524,288 in 19-bit mode, (0.88 x
VREFIO) x 2/16,777,216 in 24-bit mode, and (0.88 x
VREFIO) x 2/65536 for the MAX11060.
Power-On Reset
The serial interface, logic, digital filter, and modulator
circuits reset to zero at power-up. The power-on reset
circuit releases this reset no more than 1ms after
VDVDD rises above 2V.
OUTPUT CODE
FS = +0.88 x VREFIO
011...111
ZS = 0
011..110
-FS = -0.88 x VREFIO
000...011
000...010
000...001
000...000
111...111
1 LSB = 2(0.88 x VREFIO)
2N*
*N = 19 FOR 19-BIT TRANSFER
FUNCTION,
N = 24 FOR 24-BIT TRANSFER
FUNCTION
N = 16 FOR MAX11060
111...110
FULL-SCALE
TRANSITION
100...001
100...000
-FS
0
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 17. ADC Transfer Function
FS
FS - 3/2 LSB
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