DS1678 Datasheet, PDF (4/25 Pages) Maxim Integrated Products – Real-Time Event Recorder

DS1678 Real-Time Event Recorder
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Limits at -40°C are guaranteed by design and not production tested.
All voltages referenced to ground.
After this period, the first clock pulse is generated.
A device must initially provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of the falling edge
of SCL. The maximum t_HD:DAT need only be met if the device does not stretch the LOW period (t_LOW) of the SCL signal.
A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT > 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line t_R(MAX) + t_SU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
C_B—Total capacitance of one bus line in pF.
t_R and t_F are measured with a 1.7kΩ pullup resistor, 200pF pullup capacitor, 1.7kΩ pulldown resistor, and 5pF
pulldown capacitor.
I²C COMMUNICATION TIMING DIAGRAM
SDA
t_{B U F}
t_LOW
t_R
SCL
STOP START
t _HD:STA
t _HD:DAT
tHD:STA
tF
tH IG H
t SU:DAT
t SU:STA
REPEATED
START
t SU:STO
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