DS1678 Datasheet, PDF (20/25 Pages) Maxim Integrated Products – Real-Time Event Recorder

STATUS REGISTER (0Fh)
MSB
BIT 7
BIT 6
BIT 5
0
MEM CLR MIP
DS1678 Real-Time Event Recorder
BIT 4
CM
BIT 3
LOBAT
BIT 2
ROF
BIT 1
0
LSB
BIT 0
ALMF
Bit 6: Memory Cleared (MEM CLR). This bit indicates that the Event-Log Memory, Event Counter,
and Start Time Stamp registers are all cleared to zero. MEM CLR is cleared to zero when an event-log
mission is started (i.e., MIP = 1).
Bit 5: Mission in Progress (MIP). This bit indicates the sampling status of the DS1678. If MIP is logic
one, the device is currently on a “mission” in which it is operating in the event-logging mode. The MIP
bit is changed to logic one immediately following the activation of INT if the ME bit of the Control
Register contains a one. To immediately start an event-logging mission via the I²C bus, a one can be
written into the MIP bit and a one is automatically written into the ME bit of the Control Register.
If MIP is logic zero, the DS1678 is not currently in event-logging mode. The MIP bit transitions from
logic one to logic zero whenever event logging is stopped. Event logging is stopped when the DS1678 is
cleared by writing to the clear enable and memory clear bits, or when any memory location including the
RTC or control registers is written to during a mission. The MIP bit can also be written to logic zero by
the end user to stop event logging via the I²C bus. By writing a zero to the MIP bit and stopping the
mission, a zero is automatically written to the ME bit of the Control Register. It cannot, however, be
written to logic one to start a mission unless the MEM CLR bit is a one to signify that the memory has
been cleared.
Bit 4: Clear Memory (CM). This bit triggers the memory to be cleared if the CLR clear enable and
EOSC oscillator enable bits in the Control Register are set to one. This causes the Event-Log Memory,
Event Counter, and Start Time Stamp registers to all be cleared to zeros. Once the memory has been
cleared, the CLR enable bit and the CM bits are set to zeros, and the MEM CLR bit is set to one to allow
a new mission to begin. Clearing the memory is a two-write process to reduce the risk of accidentally
erasing the memory. The CLR bit must be set to one before the CM bit can be written to one. During the
clear memory operation, the DS1678 should not be accessed for 500µs while the memory is erased. The
MEM CLR bit should read a one before trying to access the cleared memory or registers.
Bit 3: Low-Battery Flag (LOBAT). This bit reflects the status of the backup power source connected to
the V_BAT pin. A logic one for this bit indicates an exhausted lithium energy source.
Bit 2: Rollover Flag (ROF). This bit is set to one if the RO bit of the Control Register is set to one, the
last data log memory location has been filled, and a new event has occurred, which causes the time/date
stamp to be overwritten. If RO is set to zero (rollover is disabled), the last data log memory location has
been filled, and a new event has occurred, ROF is set to one to indicate that more events have occurred
than the number of available memory locations. The event counter continues to record events, even after
the event-log memory is full. The ROF is cleared by the clear memory command.
Bit 0: Alarm Flag (ALMF). A logic one in the alarm flag bit indicates that the current time has matched
the time-of-day alarm registers. If, at the same time, the DISx bits are both logic zero, INT goes low to
issue an alarm interrupt. ALMF is a read-only bit and is cleared by accessing any of the Alarm Register
bytes either with a read or a write. Writing any memory location during a mission stops the mission. A
mission cannot be started when the DISx bits are set to zero.
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