DS1678 Datasheet, PDF (22/25 Pages) Maxim Integrated Products – Real-Time Event Recorder

DS1678 Real-Time Event Recorder
SECURITY
The DS1678 provides several measures to ensure data integrity for the end user. These security measures
are intended to prevent third-party intermediaries from tampering with the data that has been stored in the
event-log memory.
As a first security measure, the event-log memory is read-only from the perspective of the end user. The
DS1678 can write the data into these memory banks, but the end user cannot write data to individual
registers. This prevents an unscrupulous intermediary from writing false data to the DS1678. The end
user, however, can clear the contents of the event-log memory. A new mission cannot be started unless
the MEM CLR bit has been set to one to indicate that the memory and registers are cleared.
As a second security measure, changing any value in the memory including the RTC and control registers
stops event logging and clears the MIP and ME bits. The MEM CLR bit must be set to one so the
memory and registers are cleared before a new event-log mission can begin.
I²C SERIAL DATA BUS
The DS1678 supports a bidirectional I²C bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1678 operates as a slave on the I²C bus. Connections
to the bus are made via the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 6):
Data transfer can be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is HIGH are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is
HIGH, defines the STOP condition.
Data valid: The state of the data line represents valid data when, after a START condition, the data line
is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed
during the LOW period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The
number of data bytes transferred between START and STOP conditions is not limited, and is determined
by the master device. The information is transferred byte-wise and each receiver acknowledges with a
ninth bit. Within the bus specifications a standard mode (100kHz clock rate) and a fast mode (400kHz
clock rate) are defined. The DS1678 works in both modes.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the
reception of each byte. The master device must generate an extra clock pulse which is associated with this
acknowledge bit.
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